Functional Verification

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Explicit wire declaration by Virtuoso netlister

Category: Functional Verification

By stanzani
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updated over 7 years ago by alin mocanu

1 replies • 13308 views
Discussion

Efficiency of associative array

Category: Functional Verification

By Jeff000
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updated over 7 years ago by Jeff000

8 replies • 6333 views
Discussion

#ifdef #else #endif inside module instantiation in Verilog

Category: Functional Verification

By aarthymani
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updated over 7 years ago by aarthymani

8 replies • 22760 views
Discussion

Accessing Packed Arrays using Tcl Interface

Category: Functional Verification

By GaneshAMBA
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updated over 7 years ago by GaneshAMBA

2 replies • 14616 views
Discussion

Cadence 17.2 Continuous Refresh problem

Category: Functional Verification

By ajeya
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updated over 7 years ago by StephenH

1 replies • 13088 views
Discussion

How to add hook when exit from simulation?

Category: Functional Verification

By Jeff000
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updated over 7 years ago by StephenH

3 replies • 1297 views
Discussion

C code generated by the veriloga

Category: Functional Verification

By PietroUser
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updated over 7 years ago by StephenH

1 replies • 13231 views
Discussion

How to get system time in SV?

Category: Functional Verification

By Jeff000
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updated over 7 years ago by Jeff000

2 replies • 5939 views
Discussion

iprof_report_dir generated with only a hidden folder

Category: Functional Verification

By Jeff000
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updated over 7 years ago by tpylant

1 replies • 764 views
Discussion

How to increase the signal name font size in Simvision?

Category: Functional Verification

By Jeff000
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updated over 7 years ago by Jeff000

2 replies • 11203 views
Discussion

code_coverage_Error_The_design_unit _somename_has_multiple_top-level_instances_in_the_design_enabled_for_coverage

Category: Functional Verification

By MaheshKumar
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updated over 7 years ago by MaheshKumar

3 replies • 2745 views
Discussion

How to collapse and expand the group in simvision with tcl command?

Category: Functional Verification

By Jeff000
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updated over 7 years ago by Jeff000

2 replies • 3302 views
Discussion

How do I uncheck "Process statement" from sidebar in Simvision?

Category: Functional Verification

By Ncsim User 1
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updated over 7 years ago by StephenH

4 replies • 2579 views
Discussion

How do I add a compiled .a library to SV + DPI-C cosimulation?

Category: Functional Verification

By Ncsim User 1
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updated over 7 years ago by Ncsim User 1

1 replies • 13177 views
Discussion

passing IRUN command-line arguments into vsif file?

Category: Functional Verification

By xzhao
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updated over 7 years ago by Subhash Sangam

4 replies • 20615 views

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