Functional Verification

Latest Posts

Discussion

Incisive HAL user guide

Category: Functional Verification

By maheshp

$usertype
•
updated over 14 years ago by TAM1

1 replies • 19761 views
Discussion

ecov file in vmanager

Category: Functional Verification

By nishvlsi

$usertype
•
started over 14 years ago

0 replies • 13177 views
Discussion

iff on coverpoint block effecting another coverpoint with transition in the same group

Category: Functional Verification

By dambui

$usertype
•
updated over 14 years ago by Shalom B

1 replies • 17873 views
Discussion

reg pregen & postgen

Category: Functional Verification

By golson

$usertype
•
updated over 15 years ago by golson

2 replies • 1042 views
Discussion

How to preload a memory in a design using Tcl scripts in NCSIM

Category: Functional Verification

By Arrun

$usertype
•
updated over 15 years ago by Arrun

2 replies • 16729 views
Discussion

Part-Select of an Array in SystemVerilog ... Not supported by Incisive ?

Category: Functional Verification

By Almendrico

$usertype
•
updated over 15 years ago by Almendrico

3 replies • 23132 views
Discussion

event on combination of VHDL and verilog RTL path

Category: Functional Verification

By Ravisinha

$usertype
•
updated over 15 years ago by Ravisinha

2 replies • 14811 views
Discussion

functional coverage database not getting merged

Category: Functional Verification

By sautech

$usertype
•
updated over 15 years ago by sautech

3 replies • 16300 views
Discussion

merging issues in functional coverage

Category: Functional Verification

By hariharans

$usertype
•
started over 15 years ago

0 replies • 13594 views
Discussion

VR_AD, how to have a coverage for bit toggle, not value

Category: Functional Verification

By RyanLV

$usertype
•
started over 15 years ago

0 replies • 13636 views
Discussion

Adding $comment into VCD files

Category: Functional Verification

By icedancerni2

$usertype
•
updated over 15 years ago by StephenH

1 replies • 14591 views
Discussion

Help: vr_ad sequence expansion error

Category: Functional Verification

By MukundVerif

$usertype
•
updated over 15 years ago by StephenH

1 replies • 13576 views
Discussion

ncsim: How to display list of Verilog force, from inside Verilog testbench?

Category: Functional Verification

By cubicle82

$usertype
•
started over 15 years ago

0 replies • 16224 views
Discussion

end-of-test

Category: Functional Verification

By Ravisinha

$usertype
•
updated over 15 years ago by Ayush

1 replies • 14036 views
Discussion

Constrained Random Control using the OVM Command Line Package

Category: Functional Verification

By kschott

$usertype
•
started over 15 years ago

0 replies • 13732 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.