Functional Verification

Latest Posts

Discussion

iff on coverpoint block effecting another coverpoint with transition in the same group

Category: Functional Verification

By dambui
•
updated over 14 years ago by Shalom B

1 replies • 17100 views
Discussion

reg pregen & postgen

Category: Functional Verification

By golson
•
updated over 14 years ago by golson

2 replies • 891 views
Discussion

How to preload a memory in a design using Tcl scripts in NCSIM

Category: Functional Verification

By Arrun
•
updated over 14 years ago by Arrun

2 replies • 15845 views
Discussion

Part-Select of an Array in SystemVerilog ... Not supported by Incisive ?

Category: Functional Verification

By Almendrico
•
updated over 14 years ago by Almendrico

3 replies • 22035 views
Discussion

event on combination of VHDL and verilog RTL path

Category: Functional Verification

By Ravisinha
•
updated over 14 years ago by Ravisinha

2 replies • 14037 views
Discussion

functional coverage database not getting merged

Category: Functional Verification

By sautech
•
updated over 14 years ago by sautech

3 replies • 15437 views
Discussion

merging issues in functional coverage

Category: Functional Verification

By hariharans
•
started over 14 years ago

0 replies • 12976 views
Discussion

VR_AD, how to have a coverage for bit toggle, not value

Category: Functional Verification

By RyanLV
•
started over 14 years ago

0 replies • 13000 views
Discussion

Adding $comment into VCD files

Category: Functional Verification

By icedancerni2
•
updated over 14 years ago by StephenH

1 replies • 13859 views
Discussion

Help: vr_ad sequence expansion error

Category: Functional Verification

By MukundVerif
•
updated over 14 years ago by StephenH

1 replies • 12920 views
Discussion

ncsim: How to display list of Verilog force, from inside Verilog testbench?

Category: Functional Verification

By cubicle82
•
started over 14 years ago

0 replies • 15402 views
Discussion

end-of-test

Category: Functional Verification

By Ravisinha
•
updated over 14 years ago by Ayush

1 replies • 13320 views
Discussion

Constrained Random Control using the OVM Command Line Package

Category: Functional Verification

By kschott
•
started over 14 years ago

0 replies • 13016 views
Discussion

arguments to tcl file with irun

Category: Functional Verification

By hrawal
•
updated over 14 years ago by hrawal

2 replies • 31449 views
Discussion

eVC integrated with sv-ovm verification environment.

Category: Functional Verification

By arjuny
•
updated over 14 years ago by StephenH

1 replies • 12974 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.