Functional Verification

Latest Posts

Discussion

ncelab and C callable SV code for ARM

Category: Functional Verification

By jzingman

$usertype
•
started over 14 years ago

0 replies • 13777 views
Discussion

NCSIM stops simulation without giving any notice.

Category: Functional Verification

By prkroon

$usertype
•
updated over 15 years ago by prkroon

1 replies • 16673 views
Discussion

Parameterized macros in sv

Category: Functional Verification

By jzingman

$usertype
•
updated over 15 years ago by jzingman

4 replies • 17076 views
Discussion

vplan showing N/A

Category: Functional Verification

By nishvlsi

$usertype
•
started over 15 years ago

0 replies • 531 views
Discussion

.tcl file

Category: Functional Verification

By vlsiproject

$usertype
•
updated over 15 years ago by imagesensor123

1 replies • 15730 views
Discussion

Expression coverage understanding

Category: Functional Verification

By Prachi1

$usertype
•
updated over 15 years ago by Prachi1

2 replies • 18723 views
Discussion

Module coverage lower than instance coverage

Category: Functional Verification

By dmorri12

$usertype
•
started over 15 years ago

0 replies • 13961 views
Discussion

ncprotect -> VCS

Category: Functional Verification

By tonydjrx

$usertype
•
started over 15 years ago

0 replies • 2707 views
Discussion

What is the correct syntax for forcing signal in a Verilog testbench

Category: Functional Verification

By Blaise70

$usertype
•
updated over 15 years ago by Blaise70

6 replies • 38938 views
Discussion

using an event inside a TCM

Category: Functional Verification

By LATHEESH

$usertype
•
updated over 15 years ago by LATHEESH

2 replies • 14344 views
Discussion

vhpi start-of-restart callback

Category: Functional Verification

By RonCash

$usertype
•
started over 15 years ago

0 replies • 13881 views
Discussion

Parameterized Coverage...HOW?

Category: Functional Verification

By tooniz

$usertype
•
updated over 15 years ago by tpylant

2 replies • 14674 views
Discussion

How to set NoTimingCheck on a single instance in NC-Verilog

Category: Functional Verification

By bgpradeep

$usertype
•
started over 15 years ago

0 replies • 14467 views
Discussion

Ncverilog: Is there a predefined `define containing IUS version number/string?

Category: Functional Verification

By cubicle82

$usertype
•
updated over 15 years ago by StephenH

3 replies • 2555 views
Discussion

Enterprise Manager tutorial

Category: Functional Verification

By perfectus

$usertype
•
updated over 15 years ago by verify fast

7 replies • 16799 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.