Hardware/Software Co-Development, Verification and Integration

Latest Posts

Discussion

Problem with XFRM_LINEAR Subcircuit

Category: Hardware/Software Co-Development, Verification and Integration

By G Balaji

$usertype
•
updated over 16 years ago by oldmouldy

3 replies • 15679 views
Discussion

Malloc fails with exception

Category: Hardware/Software Co-Development, Verification and Integration

By alphaneo

$usertype
•
updated over 16 years ago by alphaneo

1 replies • 14033 views
Discussion

NC-Verilog Co-simulation

Category: Hardware/Software Co-Development, Verification and Integration

By mattyc

$usertype
•
updated over 16 years ago by alphaneo

1 replies • 14730 views
Discussion

Error: combinatorial path crossing multiple units drives a signal

Category: Hardware/Software Co-Development, Verification and Integration

By pingu

$usertype
•
started over 16 years ago

0 replies • 13875 views
Discussion

Integrating PSL/Verilog propertie files into a VHDL based RTL verification environment

Category: Hardware/Software Co-Development, Verification and Integration

By aymen

$usertype
•
started over 16 years ago

0 replies • 628 views
Discussion

Instability during simulation

Category: Hardware/Software Co-Development, Verification and Integration

By archive

$usertype
•
updated over 16 years ago by jhuang

1 replies • 13817 views
Discussion

Exporting task using DPI

Category: Hardware/Software Co-Development, Verification and Integration

By alphaneo

$usertype
•
updated over 16 years ago by Mickey

1 replies • 14266 views
Discussion

Online documentation/manuals

Category: Hardware/Software Co-Development, Verification and Integration

By IainM

$usertype
•
updated over 16 years ago by oldmouldy

1 replies • 9674 views
Discussion

Using mixed verilog-ams and SystemVerilog: irun vs ncvlog/ncelab/ncsim

Category: Hardware/Software Co-Development, Verification and Integration

By testing

$usertype
•
updated over 16 years ago by testing

2 replies • 2310 views
Discussion

Extracting congestion information for each Gcell

Category: Hardware/Software Co-Development, Verification and Integration

By Vaishnavi

$usertype
•
updated over 16 years ago by Vaishnavi

1 replies • 14696 views
Discussion

Fixed property help

Category: Hardware/Software Co-Development, Verification and Integration

By croc4

$usertype
•
updated over 16 years ago by croc4

2 replies • 14234 views
Discussion

Transformer Models and Libraries in PSpice and Capture

Category: Hardware/Software Co-Development, Verification and Integration

By Nils12

$usertype
•
updated over 16 years ago by oldmouldy

1 replies • 24549 views
Discussion

verilogA to verilog translation

Category: Hardware/Software Co-Development, Verification and Integration

By vlau2

$usertype
•
updated over 16 years ago by aplumb

1 replies • 14517 views
Discussion

sdr sdram testing on board

Category: Hardware/Software Co-Development, Verification and Integration

By gangireddy

$usertype
•
started over 16 years ago

0 replies • 13652 views
Discussion

Using C-to-Silicon

Category: Hardware/Software Co-Development, Verification and Integration

By marco23

$usertype
•
updated over 16 years ago by marco23

2 replies • 14445 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.