Hardware/Software Co-Development, Verification and Integration

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Discussion

i don't know how to solve it

Category: Hardware/Software Co-Development, Verification and Integration

By anhdung88
•
updated over 17 years ago by oldmouldy

1 replies • 2321 views
Discussion

Problem with XFRM_LINEAR Subcircuit

Category: Hardware/Software Co-Development, Verification and Integration

By G Balaji
•
updated over 17 years ago by oldmouldy

3 replies • 17171 views
Discussion

Malloc fails with exception

Category: Hardware/Software Co-Development, Verification and Integration

By alphaneo
•
updated over 17 years ago by alphaneo

1 replies • 15235 views
Discussion

NC-Verilog Co-simulation

Category: Hardware/Software Co-Development, Verification and Integration

By mattyc
•
updated over 17 years ago by alphaneo

1 replies • 16202 views
Discussion

Error: combinatorial path crossing multiple units drives a signal

Category: Hardware/Software Co-Development, Verification and Integration

By pingu
•
started over 17 years ago

0 replies • 14977 views
Discussion

Integrating PSL/Verilog propertie files into a VHDL based RTL verification environment

Category: Hardware/Software Co-Development, Verification and Integration

By aymen
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started over 17 years ago

0 replies • 829 views
Discussion

Instability during simulation

Category: Hardware/Software Co-Development, Verification and Integration

By archive
•
updated over 17 years ago by jhuang

1 replies • 15050 views
Discussion

Exporting task using DPI

Category: Hardware/Software Co-Development, Verification and Integration

By alphaneo
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updated over 17 years ago by Mickey

1 replies • 15500 views
Discussion

Online documentation/manuals

Category: Hardware/Software Co-Development, Verification and Integration

By IainM
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updated over 17 years ago by oldmouldy

1 replies • 10396 views
Discussion

Using mixed verilog-ams and SystemVerilog: irun vs ncvlog/ncelab/ncsim

Category: Hardware/Software Co-Development, Verification and Integration

By testing
•
updated over 17 years ago by testing

2 replies • 2855 views
Discussion

Extracting congestion information for each Gcell

Category: Hardware/Software Co-Development, Verification and Integration

By Vaishnavi
•
updated over 17 years ago by Vaishnavi

1 replies • 16052 views
Discussion

Fixed property help

Category: Hardware/Software Co-Development, Verification and Integration

By croc4
•
updated over 17 years ago by croc4

2 replies • 15580 views
Discussion

Transformer Models and Libraries in PSpice and Capture

Category: Hardware/Software Co-Development, Verification and Integration

By Nils12
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updated over 17 years ago by oldmouldy

1 replies • 27336 views
Discussion

verilogA to verilog translation

Category: Hardware/Software Co-Development, Verification and Integration

By vlau2
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updated over 17 years ago by aplumb

1 replies • 15807 views
Discussion

sdr sdram testing on board

Category: Hardware/Software Co-Development, Verification and Integration

By gangireddy
•
started over 17 years ago

0 replies • 14788 views

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