Logic Design

Latest Posts

Discussion

Forum for Low Power Discussions?

Category: Logic Design

By Rama Kishore
•
started over 8 years ago

0 replies • 12752 views
Discussion

How to determine electrical equivalence of resolved nets, with UPF 1801 standard ?

Category: Logic Design

By Rama Kishore
•
started over 8 years ago

0 replies • 13026 views
Discussion

HighConn and LowConn of input port in IEEE 1801 UPF standard

Category: Logic Design

By Rama Kishore
•
started over 8 years ago

0 replies • 15623 views
Discussion

How to set ignore for some of blackbox pins in LEC?

Category: Logic Design

By lc337199
•
updated over 8 years ago by Joshs

2 replies • 18242 views
Discussion

Synthesis in RTL Compiler Lint report

Category: Logic Design

By MickeySingh
•
updated over 8 years ago by grasshopper

1 replies • 14795 views
Discussion

SOCV

Category: Logic Design

By fitz
•
updated over 8 years ago by grasshopper

1 replies • 14595 views
Discussion

How to preserve the internal signal name in synthesis when using Cadence RTL compiler

Category: Logic Design

By rexnyu
•
updated over 8 years ago by fitz

4 replies • 18850 views
Discussion

Synthesis with multi-thread CPU

Category: Logic Design

By VoTuanMinh
•
updated over 9 years ago by grasshopper

1 replies • 15460 views
Discussion

How to handle rtl-instantiated low power cells?

Category: Logic Design

By TriStated
•
updated over 9 years ago by grasshopper

3 replies • 14410 views
Discussion

Removing external delay messages

Category: Logic Design

By menime54
•
started over 9 years ago

0 replies • 12808 views
Discussion

Scannable DFT shadow-logic insertion with register sharing around FIFOs by adding clock gating on main test clock

Category: Logic Design

By Pacher Luca
•
started over 9 years ago

0 replies • 16865 views
Discussion

Power Calculation and Average Power for large set of input combinations (in thousands)

Category: Logic Design

By mkza1002
•
updated over 9 years ago by mkza1002

9 replies • 18827 views
Discussion

How To Change Design Name in RTL Compiler

Category: Logic Design

By menime54
•
updated over 9 years ago by grasshopper

1 replies • 15466 views
Discussion

Slow Clock Problem

Category: Logic Design

By HS88
•
updated over 9 years ago by grasshopper

3 replies • 15831 views
Discussion

Adding pg pins to a netlist

Category: Logic Design

By deeps4
•
updated over 9 years ago by deeps4

4 replies • 17194 views

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