Logic Design

Latest Posts

Discussion

re-target technology node

Category: Logic Design

By DDEOTA
•
started over 11 years ago

0 replies • 12671 views
Discussion

Force RTL compiler not to optimize certain part of the design

Category: Logic Design

By rexnyu
•
updated over 11 years ago by grasshopper

1 replies • 15252 views
Discussion

What is 'comment' character for ihdl files?

Category: Logic Design

By sayn
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started over 11 years ago

0 replies • 5434 views
Discussion

where can we get the RAK

Category: Logic Design

By tanyacool
•
updated over 11 years ago by Azar990

2 replies • 14750 views
Discussion

Asynchronous FIFO design

Category: Logic Design

By abhinavpr
•
updated over 11 years ago by KennyWylies

7 replies • 20620 views
Discussion

where can i get gate.lib

Category: Logic Design

By Anasios
•
updated over 11 years ago by oldmouldy

1 replies • 15155 views
Discussion

RC: set_min/max_delay breaks the constrained paths

Category: Logic Design

By Sporadic Crash
•
updated over 11 years ago by sjoshi

3 replies • 3635 views
Discussion

What does Constant hierarchical Pin(s) means in RTL compiler?

Category: Logic Design

By Bardia B
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updated over 11 years ago by bmiller

1 replies • 7280 views
Discussion

*E,TRFILEIO: file I/O Error using textio.all library in Sigasi

Category: Logic Design

By melisanthi
•
started over 11 years ago

0 replies • 1269 views
Discussion

unwanted "\" in netlist

Category: Logic Design

By tompy
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updated over 12 years ago by tompy

2 replies • 1620 views
Discussion

The error of Synthesis

Category: Logic Design

By bravepanda
•
started over 12 years ago

0 replies • 15233 views
Discussion

Question about the multiplier

Category: Logic Design

By bravepanda
•
updated over 12 years ago by grasshopper

3 replies • 15883 views
Discussion

Library requirements during elaboration stage

Category: Logic Design

By tanyacool
•
updated over 12 years ago by tanyacool

2 replies • 13910 views
Discussion

how to define scan chains in RC

Category: Logic Design

By tanyacool
•
updated over 12 years ago by grasshopper

1 replies • 15325 views
Discussion

Include a IP netlist during Synthesis of a complete design

Category: Logic Design

By Bapaiah
•
updated over 12 years ago by Bapaiah

2 replies • 13443 views

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