Logic Design

Latest Posts

Discussion

Module name change after synthesis in RTL compiler

Category: Logic Design

By manideepa
•
updated over 9 years ago by manideepa

2 replies • 18136 views
Discussion

cadence RC area report -- how can i get the memory area information?

Category: Logic Design

By imeradio
•
updated over 9 years ago by grasshopper

1 replies • 1600 views
Discussion

SOC DFT methodology

Category: Logic Design

By CHIPS4YU
•
updated over 9 years ago by CHIPS4YU

2 replies • 15997 views
Discussion

Setting a MAX value for fan_Out ( or slew rate)

Category: Logic Design

By Medya
•
updated over 9 years ago by grasshopper

1 replies • 16566 views
Discussion

why leakage power is changing by changing activity file? I think dynamic power had a direction relation with activity file ??

Category: Logic Design

By MdS1245
•
updated over 9 years ago by Thulasi reddy

2 replies • 16413 views
Discussion

How to Synthesize Buffer Chain?

Category: Logic Design

By Kraj
•
updated over 9 years ago by grasshopper

1 replies • 15811 views
Discussion

Forum for Low Power Discussions?

Category: Logic Design

By Rama Kishore
•
started over 9 years ago

0 replies • 14446 views
Discussion

How to determine electrical equivalence of resolved nets, with UPF 1801 standard ?

Category: Logic Design

By Rama Kishore
•
started over 9 years ago

0 replies • 14786 views
Discussion

HighConn and LowConn of input port in IEEE 1801 UPF standard

Category: Logic Design

By Rama Kishore
•
started over 9 years ago

0 replies • 17927 views
Discussion

How to set ignore for some of blackbox pins in LEC?

Category: Logic Design

By lc337199
•
updated over 10 years ago by Joshs

2 replies • 21237 views
Discussion

Synthesis in RTL Compiler Lint report

Category: Logic Design

By MickeySingh
•
updated over 10 years ago by grasshopper

1 replies • 17040 views
Discussion

SOCV

Category: Logic Design

By fitz
•
updated over 10 years ago by grasshopper

1 replies • 17082 views
Discussion

How to preserve the internal signal name in synthesis when using Cadence RTL compiler

Category: Logic Design

By rexnyu
•
updated over 10 years ago by fitz

4 replies • 22715 views
Discussion

Synthesis with multi-thread CPU

Category: Logic Design

By VoTuanMinh
•
updated over 10 years ago by grasshopper

1 replies • 17836 views
Discussion

How to handle rtl-instantiated low power cells?

Category: Logic Design

By TriStated
•
updated over 10 years ago by grasshopper

3 replies • 16690 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.