Logic Design

Latest Posts

Discussion

why leakage power is changing by changing activity file? I think dynamic power had a direction relation with activity file ??

Category: Logic Design

By MdS1245
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updated over 9 years ago by Thulasi reddy

2 replies • 16215 views
Discussion

How to Synthesize Buffer Chain?

Category: Logic Design

By Kraj
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updated over 9 years ago by grasshopper

1 replies • 15657 views
Discussion

Forum for Low Power Discussions?

Category: Logic Design

By Rama Kishore
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started over 9 years ago

0 replies • 14360 views
Discussion

How to determine electrical equivalence of resolved nets, with UPF 1801 standard ?

Category: Logic Design

By Rama Kishore
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started over 9 years ago

0 replies • 14684 views
Discussion

HighConn and LowConn of input port in IEEE 1801 UPF standard

Category: Logic Design

By Rama Kishore
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started over 9 years ago

0 replies • 17679 views
Discussion

How to set ignore for some of blackbox pins in LEC?

Category: Logic Design

By lc337199
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updated over 9 years ago by Joshs

2 replies • 20792 views
Discussion

Synthesis in RTL Compiler Lint report

Category: Logic Design

By MickeySingh
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updated over 9 years ago by grasshopper

1 replies • 16862 views
Discussion

SOCV

Category: Logic Design

By fitz
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updated over 9 years ago by grasshopper

1 replies • 16778 views
Discussion

How to preserve the internal signal name in synthesis when using Cadence RTL compiler

Category: Logic Design

By rexnyu
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updated over 9 years ago by fitz

4 replies • 22066 views
Discussion

Synthesis with multi-thread CPU

Category: Logic Design

By VoTuanMinh
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updated over 10 years ago by grasshopper

1 replies • 17606 views
Discussion

How to handle rtl-instantiated low power cells?

Category: Logic Design

By TriStated
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updated over 10 years ago by grasshopper

3 replies • 16465 views
Discussion

Removing external delay messages

Category: Logic Design

By menime54
•
started over 10 years ago

0 replies • 14456 views
Discussion

Scannable DFT shadow-logic insertion with register sharing around FIFOs by adding clock gating on main test clock

Category: Logic Design

By Pacher Luca
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started over 10 years ago

0 replies • 19293 views
Discussion

Power Calculation and Average Power for large set of input combinations (in thousands)

Category: Logic Design

By mkza1002
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updated over 10 years ago by mkza1002

9 replies • 21988 views
Discussion

How To Change Design Name in RTL Compiler

Category: Logic Design

By menime54
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updated over 10 years ago by grasshopper

1 replies • 17762 views

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