• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Logic Design
CDNS - double leaderboard script

Logic Design

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Latest Posts

  • Create a new Post
  • Discussion

    SOC DFT methodology

    Category: Logic Design

    By CHIPS4YU

    •

    updated over 9 years ago by CHIPS4YU

    2 replies • 15912 views
  • Discussion

    Setting a MAX value for fan_Out ( or slew rate)

    Category: Logic Design

    By Medya

    •

    updated over 9 years ago by grasshopper

    1 replies • 16477 views
  • Discussion

    why leakage power is changing by changing activity file? I think dynamic power had a direction relation with activity file ??

    Category: Logic Design

    By MdS1245

    •

    updated over 9 years ago by Thulasi reddy

    2 replies • 16325 views
  • Discussion

    How to Synthesize Buffer Chain?

    Category: Logic Design

    By Kraj

    •

    updated over 9 years ago by grasshopper

    1 replies • 15743 views
  • Discussion

    Forum for Low Power Discussions?

    Category: Logic Design

    By Rama Kishore

    •

    started over 9 years ago

    0 replies • 14422 views
  • Discussion

    How to determine electrical equivalence of resolved nets, with UPF 1801 standard ?

    Category: Logic Design

    By Rama Kishore

    •

    started over 9 years ago

    0 replies • 14751 views
  • Discussion

    HighConn and LowConn of input port in IEEE 1801 UPF standard

    Category: Logic Design

    By Rama Kishore

    •

    started over 9 years ago

    0 replies • 17819 views
  • Discussion

    How to set ignore for some of blackbox pins in LEC?

    Category: Logic Design

    By lc337199

    •

    updated over 9 years ago by Joshs

    2 replies • 21022 views
  • Discussion

    Synthesis in RTL Compiler Lint report

    Category: Logic Design

    By MickeySingh

    •

    updated over 9 years ago by grasshopper

    1 replies • 16972 views
  • Discussion

    SOCV

    Category: Logic Design

    By fitz

    •

    updated over 9 years ago by grasshopper

    1 replies • 16968 views
  • Discussion

    How to preserve the internal signal name in synthesis when using Cadence RTL compiler

    Category: Logic Design

    By rexnyu

    •

    updated over 9 years ago by fitz

    4 replies • 22526 views
  • Discussion

    Synthesis with multi-thread CPU

    Category: Logic Design

    By VoTuanMinh

    •

    updated over 10 years ago by grasshopper

    1 replies • 17747 views
  • Discussion

    How to handle rtl-instantiated low power cells?

    Category: Logic Design

    By TriStated

    •

    updated over 10 years ago by grasshopper

    3 replies • 16601 views
  • Discussion

    Removing external delay messages

    Category: Logic Design

    By menime54

    •

    started over 10 years ago

    0 replies • 14527 views
  • Discussion

    Scannable DFT shadow-logic insertion with register sharing around FIFOs by adding clock gating on main test clock

    Category: Logic Design

    By Pacher Luca

    •

    started over 10 years ago

    0 replies • 19528 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information