Logic Design

Latest Posts

Discussion

Delay in Or cad pspice

Category: Logic Design

By amrita1503
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updated over 8 years ago by amrita1503

2 replies • 16518 views
Discussion

Hierarchical design component used report

Category: Logic Design

By chillman
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started over 8 years ago

0 replies • 14475 views
Discussion

Super threading error inside RTL Compiler

Category: Logic Design

By as90
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started over 8 years ago

0 replies • 15798 views
Discussion

Timing analysis in RTL Compiler

Category: Logic Design

By as90
•
updated over 8 years ago by as90

2 replies • 16009 views
Discussion

Missing clock arrival for one transition because a timing arc

Category: Logic Design

By TungVo
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started over 8 years ago

0 replies • 16969 views
Discussion

NCVLOG error NPITEM -- Not a valid package item: 'interface_declaration' [SystemVerilog]

Category: Logic Design

By Iovi
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started over 8 years ago

0 replies • 1615 views
Discussion

Warnings when synthesis using RTL compiler

Category: Logic Design

By Greatrebel
•
updated over 8 years ago by grasshopper

5 replies • 19785 views
Discussion

UPF to CPF conversion

Category: Logic Design

By vicky
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updated over 9 years ago by pavannelluri

14 replies • 30969 views
Discussion

Genus:design elaboration: unusable library cells?

Category: Logic Design

By remi pallas
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started over 9 years ago

0 replies • 1865 views
Discussion

Genus: design elaboration : unusable library cells?

Category: Logic Design

By remi pallas
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started over 9 years ago

0 replies • 15004 views
Discussion

VCD and irun

Category: Logic Design

By ganeshK2012
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updated over 9 years ago by cirosantilli

2 replies • 18473 views
Discussion

Module name change after synthesis in RTL compiler

Category: Logic Design

By manideepa
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updated over 9 years ago by manideepa

2 replies • 17891 views
Discussion

cadence RC area report -- how can i get the memory area information?

Category: Logic Design

By imeradio
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updated over 9 years ago by grasshopper

1 replies • 1488 views
Discussion

SOC DFT methodology

Category: Logic Design

By CHIPS4YU
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updated over 9 years ago by CHIPS4YU

2 replies • 15813 views
Discussion

Setting a MAX value for fan_Out ( or slew rate)

Category: Logic Design

By Medya
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updated over 9 years ago by grasshopper

1 replies • 16283 views

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