Logic Design

Latest Posts

Discussion

Super threading error inside RTL Compiler

Category: Logic Design

By as90
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started over 7 years ago

0 replies • 14032 views
Discussion

Timing analysis in RTL Compiler

Category: Logic Design

By as90
•
updated over 7 years ago by as90

2 replies • 14022 views
Discussion

Missing clock arrival for one transition because a timing arc

Category: Logic Design

By TungVo
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started over 7 years ago

0 replies • 15094 views
Discussion

NCVLOG error NPITEM -- Not a valid package item: 'interface_declaration' [SystemVerilog]

Category: Logic Design

By Iovi
•
started over 7 years ago

0 replies • 1344 views
Discussion

Warnings when synthesis using RTL compiler

Category: Logic Design

By Greatrebel
•
updated over 8 years ago by grasshopper

5 replies • 17288 views
Discussion

UPF to CPF conversion

Category: Logic Design

By vicky
•
updated over 8 years ago by pavannelluri

14 replies • 26418 views
Discussion

Genus:design elaboration: unusable library cells?

Category: Logic Design

By remi pallas
•
started over 8 years ago

0 replies • 1468 views
Discussion

Genus: design elaboration : unusable library cells?

Category: Logic Design

By remi pallas
•
started over 8 years ago

0 replies • 13362 views
Discussion

VCD and irun

Category: Logic Design

By ganeshK2012
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updated over 8 years ago by cirosantilli

2 replies • 16328 views
Discussion

Module name change after synthesis in RTL compiler

Category: Logic Design

By manideepa
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updated over 8 years ago by manideepa

2 replies • 15751 views
Discussion

cadence RC area report -- how can i get the memory area information?

Category: Logic Design

By imeradio
•
updated over 8 years ago by grasshopper

1 replies • 1153 views
Discussion

SOC DFT methodology

Category: Logic Design

By CHIPS4YU
•
updated over 8 years ago by CHIPS4YU

2 replies • 13857 views
Discussion

Setting a MAX value for fan_Out ( or slew rate)

Category: Logic Design

By Medya
•
updated over 8 years ago by grasshopper

1 replies • 14173 views
Discussion

why leakage power is changing by changing activity file? I think dynamic power had a direction relation with activity file ??

Category: Logic Design

By MdS1245
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updated over 8 years ago by Thulasi reddy

2 replies • 14172 views
Discussion

How to Synthesize Buffer Chain?

Category: Logic Design

By Kraj
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updated over 8 years ago by grasshopper

1 replies • 13754 views

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