Logic Design

Is there a way to set the `default_nettype directive through the command-line when running irun?

Category: Logic Design

Genus Synthesis - Cost Groups

Category: Logic Design

Delay in Or cad pspice

Category: Logic Design

Hierarchical design component used report

Category: Logic Design

Super threading error inside RTL Compiler

Category: Logic Design

Timing analysis in RTL Compiler

Category: Logic Design

Missing clock arrival for one transition because a timing arc

Category: Logic Design

NCVLOG error NPITEM -- Not a valid package item: 'interface_declaration' [SystemVerilog]

Category: Logic Design

Warnings when synthesis using RTL compiler

Category: Logic Design

UPF to CPF conversion

Category: Logic Design

Genus:design elaboration: unusable library cells?

Category: Logic Design

Genus: design elaboration : unusable library cells?

Category: Logic Design

VCD and irun

Category: Logic Design

Module name change after synthesis in RTL compiler

Category: Logic Design

cadence RC area report -- how can i get the memory area information?

Category: Logic Design