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Logic Design

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  • Discussion

    List of Highest Fanouts

    Category: Logic Design

    By GeorgeGG

    •

    started over 7 years ago

    0 replies • 14817 views
  • Discussion

    problem with "REPORT RULE CHECK" command using conformal

    Category: Logic Design

    By zohaibhassan

    •

    updated over 7 years ago by zohaibhassan

    3 replies • 7173 views
  • Discussion

    Conformal ECO use cell out of spare(NO_MAP)

    Category: Logic Design

    By Ben Xu

    •

    started over 7 years ago

    0 replies • 1556 views
  • Discussion

    CONFORMAL ECO : SPARE CELLS NOT MAPPED

    Category: Logic Design

    By NabilE

    •

    started over 7 years ago

    0 replies • 15942 views
  • Discussion

    functional equivalence check between system verilog and schematic

    Category: Logic Design

    By SatendraMaurya

    •

    started over 7 years ago

    0 replies • 15272 views
  • Discussion

    Formatting of concept HDL schematic pages

    Category: Logic Design

    By akmo25

    •

    started over 7 years ago

    0 replies • 14918 views
  • Discussion

    Error in Cadence RTL Compiler when estimating Power using VCD

    Category: Logic Design

    By shaunisu

    •

    started over 7 years ago

    0 replies • 15695 views
  • Discussion

    for choosing the frequency range of any digital circuit

    Category: Logic Design

    By jayakandpal

    •

    started over 7 years ago

    0 replies • 14514 views
  • Discussion

    RTL compiler crash

    Category: Logic Design

    By shaunisu

    •

    started over 7 years ago

    0 replies • 15564 views
  • Discussion

    What does area reported by RTL compiler mean?

    Category: Logic Design

    By rexnyu

    •

    updated over 7 years ago by Andrew Beckett

    6 replies • 38508 views
  • Discussion

    Differences between "report power" and "report scan_power"

    Category: Logic Design

    By nokta

    •

    started over 8 years ago

    0 replies • 2313 views
  • Discussion

    Irun driver contention with SystemVerilog port defaults (15.20.001)

    Category: Logic Design

    By Palaparthy

    •

    started over 8 years ago

    0 replies • 15096 views
  • Discussion

    RC compiler and ports consisting of arrays of vectors

    Category: Logic Design

    By MarkusK

    •

    updated over 8 years ago by MarkusK

    2 replies • 16101 views
  • Discussion

    port array synthesis

    Category: Logic Design

    By olalivier

    •

    started over 8 years ago

    0 replies • 16911 views
  • Discussion

    Genus UI - How to set attribute?

    Category: Logic Design

    By mbrandalero

    •

    started over 8 years ago

    0 replies • 7559 views
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