Logic Design

Latest Posts

Discussion

Error in Cadence RTL Compiler when estimating Power using VCD

Category: Logic Design

By shaunisu

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started over 6 years ago

0 replies • 14313 views
Discussion

for choosing the frequency range of any digital circuit

Category: Logic Design

By jayakandpal

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started over 6 years ago

0 replies • 13171 views
Discussion

RTL compiler crash

Category: Logic Design

By shaunisu

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started over 6 years ago

0 replies • 14097 views
Discussion

What does area reported by RTL compiler mean?

Category: Logic Design

By rexnyu

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updated over 6 years ago by Andrew Beckett

6 replies • 33599 views
Discussion

Differences between "report power" and "report scan_power"

Category: Logic Design

By nokta

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started over 7 years ago

0 replies • 1623 views
Discussion

Irun driver contention with SystemVerilog port defaults (15.20.001)

Category: Logic Design

By Palaparthy

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started over 7 years ago

0 replies • 13721 views
Discussion

RC compiler and ports consisting of arrays of vectors

Category: Logic Design

By MarkusK

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updated over 7 years ago by MarkusK

2 replies • 14477 views
Discussion

port array synthesis

Category: Logic Design

By olalivier

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started over 7 years ago

0 replies • 15188 views
Discussion

Genus UI - How to set attribute?

Category: Logic Design

By mbrandalero

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started over 7 years ago

0 replies • 6222 views
Discussion

Genus : Auto_ungroup breaks functionality

Category: Logic Design

By Schriek

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started over 7 years ago

0 replies • 14639 views
Discussion

Problems with simulating counter chips

Category: Logic Design

By zfan

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started over 7 years ago

0 replies • 13481 views
Discussion

Is there a way to set the `default_nettype directive through the command-line when running irun?

Category: Logic Design

By crclayton

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started over 7 years ago

0 replies • 14575 views
Discussion

Genus Synthesis - Cost Groups

Category: Logic Design

By Heaton15

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started over 7 years ago

0 replies • 3828 views
Discussion

Delay in Or cad pspice

Category: Logic Design

By amrita1503

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updated over 7 years ago by amrita1503

2 replies • 15131 views
Discussion

Hierarchical design component used report

Category: Logic Design

By chillman

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started over 7 years ago

0 replies • 13213 views

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