Logic Design

Latest Posts

Discussion

About SDF file after synthesis in Genus Tool

Category: Logic Design

By LiGer
•
started over 6 years ago

0 replies • 17930 views
Discussion

Simvision

Category: Logic Design

By FNaqvi
•
started over 6 years ago

0 replies • 16600 views
Discussion

How to dump waveform, fsdb in SimVision?

Category: Logic Design

By achang
•
started over 6 years ago

0 replies • 24482 views
Discussion

GENUS can't handle parameterized ports?

Category: Logic Design

By GGobieski
•
started over 6 years ago

0 replies • 3103 views
Discussion

genus include `define file

Category: Logic Design

By saw235
•
updated over 6 years ago by saw235

2 replies • 22735 views
Discussion

allegro 16.6 pcb export parameters error

Category: Logic Design

By solutions
•
started over 6 years ago

0 replies • 15103 views
Discussion

SystemVerilog package used inside VHDL-2008 design?

Category: Logic Design

By Michal Kajan
•
started over 7 years ago

0 replies • 15959 views
Discussion

How to customize default_hdl_checks/rules in CCD conformal constraint designer

Category: Logic Design

By mirzaaur
•
started over 7 years ago

0 replies • 1596 views
Discussion

using ModelSim/QuestaSim VCD file in RTL compiler

Category: Logic Design

By dkhan
•
updated over 7 years ago by shvd

4 replies • 8848 views
Discussion

Post-synthesis Simulation Failing when lp_insert_clock_gating true

Category: Logic Design

By GGobieski
•
updated over 7 years ago by GGobieski

1 replies • 17271 views
Discussion

Unable to map design without a suitable latch. [MAP-3] [synthesize]

Category: Logic Design

By 20050710212
•
updated over 7 years ago by wickjohn

6 replies • 25026 views
Discussion

Mouse wheel and [i][o] button doesn't zoom

Category: Logic Design

By phanvandung
•
started over 7 years ago

0 replies • 1929 views
Discussion

Reuse of Schematics across different Projects

Category: Logic Design

By akmo25
•
started over 7 years ago

0 replies • 15047 views
Discussion

stretching LOW pulse signal for extra 100ns

Category: Logic Design

By Iaf22
•
started over 7 years ago

0 replies • 15047 views
Discussion

Genus synthesis syntax Foreach

Category: Logic Design

By yann06
•
updated over 7 years ago by GeorgeGG

1 replies • 16601 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.