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Logic Design

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  • Discussion

    How to dump waveform, fsdb in SimVision?

    Category: Logic Design

    By achang

    •

    started over 6 years ago

    0 replies • 24360 views
  • Discussion

    GENUS can't handle parameterized ports?

    Category: Logic Design

    By GGobieski

    •

    started over 6 years ago

    0 replies • 2989 views
  • Discussion

    genus include `define file

    Category: Logic Design

    By saw235

    •

    updated over 6 years ago by saw235

    2 replies • 22502 views
  • Discussion

    allegro 16.6 pcb export parameters error

    Category: Logic Design

    By solutions

    •

    started over 6 years ago

    0 replies • 15072 views
  • Discussion

    SystemVerilog package used inside VHDL-2008 design?

    Category: Logic Design

    By Michal Kajan

    •

    started over 6 years ago

    0 replies • 15924 views
  • Discussion

    How to customize default_hdl_checks/rules in CCD conformal constraint designer

    Category: Logic Design

    By mirzaaur

    •

    started over 6 years ago

    0 replies • 1554 views
  • Discussion

    using ModelSim/QuestaSim VCD file in RTL compiler

    Category: Logic Design

    By dkhan

    •

    updated over 6 years ago by shvd

    4 replies • 8649 views
  • Discussion

    Post-synthesis Simulation Failing when lp_insert_clock_gating true

    Category: Logic Design

    By GGobieski

    •

    updated over 7 years ago by GGobieski

    1 replies • 17173 views
  • Discussion

    Unable to map design without a suitable latch. [MAP-3] [synthesize]

    Category: Logic Design

    By 20050710212

    •

    updated over 7 years ago by wickjohn

    6 replies • 24886 views
  • Discussion

    Mouse wheel and [i][o] button doesn't zoom

    Category: Logic Design

    By phanvandung

    •

    started over 7 years ago

    0 replies • 1871 views
  • Discussion

    Reuse of Schematics across different Projects

    Category: Logic Design

    By akmo25

    •

    started over 7 years ago

    0 replies • 15015 views
  • Discussion

    stretching LOW pulse signal for extra 100ns

    Category: Logic Design

    By Iaf22

    •

    started over 7 years ago

    0 replies • 15007 views
  • Discussion

    Genus synthesis syntax Foreach

    Category: Logic Design

    By yann06

    •

    updated over 7 years ago by GeorgeGG

    1 replies • 16533 views
  • Discussion

    List of Highest Fanouts

    Category: Logic Design

    By GeorgeGG

    •

    started over 7 years ago

    0 replies • 14776 views
  • Discussion

    problem with "REPORT RULE CHECK" command using conformal

    Category: Logic Design

    By zohaibhassan

    •

    updated over 7 years ago by zohaibhassan

    3 replies • 6995 views
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