Logic Design

Latest Posts

Discussion

SystemVerilog package used inside VHDL-2008 design?

Category: Logic Design

By Michal Kajan

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started over 6 years ago

0 replies • 14547 views
Discussion

How to customize default_hdl_checks/rules in CCD conformal constraint designer

Category: Logic Design

By mirzaaur

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started over 6 years ago

0 replies • 1280 views
Discussion

using ModelSim/QuestaSim VCD file in RTL compiler

Category: Logic Design

By dkhan

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updated over 6 years ago by shvd

4 replies • 7054 views
Discussion

Post-synthesis Simulation Failing when lp_insert_clock_gating true

Category: Logic Design

By GGobieski

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updated over 6 years ago by GGobieski

1 replies • 15310 views
Discussion

Unable to map design without a suitable latch. [MAP-3] [synthesize]

Category: Logic Design

By 20050710212

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updated over 6 years ago by wickjohn

6 replies • 22608 views
Discussion

Mouse wheel and [i][o] button doesn't zoom

Category: Logic Design

By phanvandung

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started over 6 years ago

0 replies • 1449 views
Discussion

Reuse of Schematics across different Projects

Category: Logic Design

By akmo25

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started over 6 years ago

0 replies • 13685 views
Discussion

stretching LOW pulse signal for extra 100ns

Category: Logic Design

By Iaf22

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started over 6 years ago

0 replies • 13683 views
Discussion

Genus synthesis syntax Foreach

Category: Logic Design

By yann06

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updated over 6 years ago by GeorgeGG

1 replies • 14866 views
Discussion

List of Highest Fanouts

Category: Logic Design

By GeorgeGG

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started over 6 years ago

0 replies • 13458 views
Discussion

problem with "REPORT RULE CHECK" command using conformal

Category: Logic Design

By zohaibhassan

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updated over 6 years ago by zohaibhassan

3 replies • 5602 views
Discussion

Conformal ECO use cell out of spare(NO_MAP)

Category: Logic Design

By Ben Xu

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started over 6 years ago

0 replies • 1242 views
Discussion

CONFORMAL ECO : SPARE CELLS NOT MAPPED

Category: Logic Design

By NabilE

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started over 6 years ago

0 replies • 14354 views
Discussion

functional equivalence check between system verilog and schematic

Category: Logic Design

By SatendraMaurya

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started over 6 years ago

0 replies • 13902 views
Discussion

Formatting of concept HDL schematic pages

Category: Logic Design

By akmo25

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started over 6 years ago

0 replies • 13555 views

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