Logic Design

Power Calculation and Average Power for large set of input combinations (in thousands)

Category: Logic Design

How To Change Design Name in RTL Compiler

Category: Logic Design

Slow Clock Problem

Category: Logic Design

Adding pg pins to a netlist

Category: Logic Design

RTL Compiler functions with regexp

Category: Logic Design

RTL Compiler command questions: pwd, multicore options, and program name

Category: Logic Design

What is the usage of memory library from the PDK?

Category: Logic Design

Not mapped points in LEC when using DC netlist

Category: Logic Design

check clock_gating gives 0 gated flip-flops after synthesize

Category: Logic Design

clock gating timing report with synthesized ICG cell

Category: Logic Design

RC Physical Flow - Spare Module

Category: Logic Design

do I need to use write_hdl -lec for equivalence check ?

Category: Logic Design

How to connect a common test port to all the CG cells for clock gating?

Category: Logic Design

Low power flow. State retention problem.

Category: Logic Design

RTL Compiler synthesis with inference to a custom cell

Category: Logic Design