Logic Design

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Discussion

Adding pg pins to a netlist

Category: Logic Design

By deeps4

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updated over 10 years ago by deeps4

4 replies • 18704 views
Discussion

RTL Compiler functions with regexp

Category: Logic Design

By menime54

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updated over 10 years ago by grasshopper

3 replies • 16144 views
Discussion

RTL Compiler command questions: pwd, multicore options, and program name

Category: Logic Design

By menime54

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updated over 10 years ago by grasshopper

1 replies • 16474 views
Discussion

What is the usage of memory library from the PDK?

Category: Logic Design

By dogrush

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updated over 10 years ago by grasshopper

1 replies • 14671 views
Discussion

Not mapped points in LEC when using DC netlist

Category: Logic Design

By Adi Mashiah

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started over 10 years ago

0 replies • 14706 views
Discussion

check clock_gating gives 0 gated flip-flops after synthesize

Category: Logic Design

By zczc99

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updated over 10 years ago by grasshopper

3 replies • 16562 views
Discussion

clock gating timing report with synthesized ICG cell

Category: Logic Design

By zczc99

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started over 10 years ago

0 replies • 17966 views
Discussion

RC Physical Flow - Spare Module

Category: Logic Design

By Yemelya

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updated over 10 years ago by grasshopper

1 replies • 1207 views
Discussion

do I need to use write_hdl -lec for equivalence check ?

Category: Logic Design

By zczc99

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updated over 10 years ago by grasshopper

1 replies • 1442 views
Discussion

How to connect a common test port to all the CG cells for clock gating?

Category: Logic Design

By zczc99

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updated over 10 years ago by grasshopper

1 replies • 15008 views
Discussion

Low power flow. State retention problem.

Category: Logic Design

By tfanni

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started over 10 years ago

0 replies • 14274 views
Discussion

RTL Compiler synthesis with inference to a custom cell

Category: Logic Design

By jjgs

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updated over 10 years ago by grasshopper

1 replies • 15834 views
Discussion

LEC - MOS direction and abstract logic error

Category: Logic Design

By sacmax

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started over 10 years ago

0 replies • 1103 views
Discussion

Multiplier Selection in RTL compiler

Category: Logic Design

By AliShami

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updated over 10 years ago by leapfrog

2 replies • 16503 views
Discussion

Conformal LEC hier_compare only on 1 module

Category: Logic Design

By Matt Hutson

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updated over 10 years ago by Matt Hutson

2 replies • 17850 views

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