Logic Design

Latest Posts

Discussion

Low power flow. State retention problem.

Category: Logic Design

By tfanni
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started over 11 years ago

0 replies • 15120 views
Discussion

RTL Compiler synthesis with inference to a custom cell

Category: Logic Design

By jjgs
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updated over 11 years ago by grasshopper

1 replies • 16780 views
Discussion

LEC - MOS direction and abstract logic error

Category: Logic Design

By sacmax
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started over 11 years ago

0 replies • 1270 views
Discussion

Multiplier Selection in RTL compiler

Category: Logic Design

By AliShami
•
updated over 11 years ago by leapfrog

2 replies • 17570 views
Discussion

Conformal LEC hier_compare only on 1 module

Category: Logic Design

By Matt Hutson
•
updated over 11 years ago by Matt Hutson

2 replies • 19291 views
Discussion

Find the dynamic power from incisive which depends on the testbench

Category: Logic Design

By raja92
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updated over 11 years ago by grasshopper

1 replies • 15213 views
Discussion

Design entry hdl

Category: Logic Design

By Danil3402
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updated over 11 years ago by grasshopper

1 replies • 5719 views
Discussion

Digital library for RTL compiler

Category: Logic Design

By mhkvy4
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updated over 11 years ago by grasshopper

2 replies • 15714 views
Discussion

RTL compiler error

Category: Logic Design

By Jinesh K B
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updated over 11 years ago by grasshopper

1 replies • 15576 views
Discussion

Using RC to estimate leakage & dynamic power from different synthesis runs

Category: Logic Design

By kenearth
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updated over 11 years ago by uma1147

1 replies • 1776 views
Discussion

How to compare 2 design entry HDL schematic?

Category: Logic Design

By maberu
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updated over 11 years ago by grasshopper

1 replies • 15760 views
Discussion

conformal lec : dump mapped points

Category: Logic Design

By HariPV
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started over 11 years ago

0 replies • 15534 views
Discussion

RC response[TUI-39]after "report clock_gating"

Category: Logic Design

By cwwang
•
updated over 12 years ago by cwwang

2 replies • 1841 views
Discussion

Using multiple libraries - mixed elaboration flow

Category: Logic Design

By drovak
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started over 12 years ago

0 replies • 2212 views
Discussion

Mining information from RTL Compiler log file.

Category: Logic Design

By sgauria
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started over 12 years ago

0 replies • 14692 views

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