Logic Design

Latest Posts

Discussion

how to synthesize delay elements in RTL complier

Category: Logic Design

By micro469

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updated over 11 years ago by grasshopper

3 replies • 16934 views
Discussion

unmapped points with Conformal

Category: Logic Design

By nozuey

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started over 11 years ago

0 replies • 15214 views
Discussion

How to force a small gate structure during RTL Compiler synthesis?

Category: Logic Design

By rexnyu

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started over 11 years ago

0 replies • 14025 views
Discussion

Avoid race condition at SPI_slave synthesis

Category: Logic Design

By alphus

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started over 11 years ago

0 replies • 5430 views
Discussion

Unsupported SDC Commands(remove_attribute) in RC

Category: Logic Design

By doydodo

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started over 11 years ago

0 replies • 642 views
Discussion

How to simulate after synthesis in NC launch or NC sim

Category: Logic Design

By micro469

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updated over 11 years ago by grasshopper

1 replies • 15679 views
Discussion

conformal LEC

Category: Logic Design

By Indira S

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started over 11 years ago

0 replies • 14044 views
Discussion

clock gating in RC

Category: Logic Design

By doydodo

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updated over 11 years ago by bmiller

1 replies • 15875 views
Discussion

Conformal ECO - Equivalanece check

Category: Logic Design

By Prashant M

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started over 11 years ago

0 replies • 1288 views
Discussion

external delay

Category: Logic Design

By IBKRAJU

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updated over 11 years ago by grasshopper

1 replies • 16921 views
Discussion

Blackboxing in Conformal LEC.

Category: Logic Design

By Bhawan

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started over 11 years ago

0 replies • 14352 views
Discussion

Reading HDL files in RC

Category: Logic Design

By archive

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updated over 11 years ago by nagarjunsingir

4 replies • 18238 views
Discussion

how to find power of a design based on inputs given to the design using cadence

Category: Logic Design

By samhitha nr

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updated over 11 years ago by grasshopper

1 replies • 14182 views
Discussion

Help on LEC failure between compile netlist vs. compile_incr netlist from DC

Category: Logic Design

By r u verified

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started over 11 years ago

0 replies • 14016 views
Discussion

CIS DB source

Category: Logic Design

By dpiccardi

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started over 11 years ago

0 replies • 14038 views

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