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Logic Design

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  • Discussion

    Problem occurs when reading vcd in RTL Compiler

    Category: Logic Design

    By rexnyu

    •

    updated over 13 years ago by rexnyu

    5 replies • 20445 views
  • Discussion

    Where is 7400.olb ?

    Category: Logic Design

    By ArealPerson

    •

    updated over 13 years ago by oldmouldy

    1 replies • 15879 views
  • Discussion

    Error : Verilog-2001 feature.

    Category: Logic Design

    By rexnyu

    •

    updated over 13 years ago by rexnyu

    1 replies • 15650 views
  • Discussion

    synthesis warning of undriven signal

    Category: Logic Design

    By projectd2007

    •

    updated over 13 years ago by grasshopper

    1 replies • 19546 views
  • Discussion

    RC ; sdc ; load_of

    Category: Logic Design

    By Yemelya

    •

    updated over 13 years ago by grasshopper

    5 replies • 19271 views
  • Discussion

    Warning during RTL Synthesis

    Category: Logic Design

    By Arslan

    •

    updated over 13 years ago by admin

    4 replies • 19512 views
  • Discussion

    Difference betweeen synthesize- generic, mapped, placed in RC

    Category: Logic Design

    By ChInNi miSSing

    •

    updated over 13 years ago by ChennaKesava

    2 replies • 5417 views
  • Discussion

    Report all the flops using a particular clock

    Category: Logic Design

    By beginer

    •

    started over 13 years ago

    0 replies • 15699 views
  • Discussion

    Which VDD and Ground sources?

    Category: Logic Design

    By FrancisFogarty

    •

    started over 13 years ago

    0 replies • 14366 views
  • Discussion

    rigid flex

    Category: Logic Design

    By runu

    •

    started over 13 years ago

    0 replies • 14514 views
  • Discussion

    Disable Scan Shift Enable in Functional Mode

    Category: Logic Design

    By Terry2000

    •

    updated over 13 years ago by bmiller

    3 replies • 19391 views
  • Discussion

    Multi Mode synthesis v/s Multi Corner synthesis

    Category: Logic Design

    By tanyacool

    •

    started over 13 years ago

    0 replies • 2113 views
  • Discussion

    RTL Compiler Hierarchical Flow

    Category: Logic Design

    By lvcargnini

    •

    updated over 13 years ago by grasshopper

    1 replies • 15751 views
  • Discussion

    Getting Error during Shadow logic insetion in share mode

    Category: Logic Design

    By ardas21

    •

    started over 13 years ago

    0 replies • 14552 views
  • Discussion

    Lowpower : CPF Compiler support.

    Category: Logic Design

    By NTlp

    •

    updated over 13 years ago by grasshopper

    6 replies • 18493 views
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