Logic Design

Latest Posts

Discussion

Difference betweeen synthesize- generic, mapped, placed in RC

Category: Logic Design

By ChInNi miSSing
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updated over 12 years ago by ChennaKesava

2 replies • 4524 views
Discussion

Report all the flops using a particular clock

Category: Logic Design

By beginer
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started over 12 years ago

0 replies • 13774 views
Discussion

Which VDD and Ground sources?

Category: Logic Design

By FrancisFogarty
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started over 12 years ago

0 replies • 12645 views
Discussion

rigid flex

Category: Logic Design

By runu
•
started over 12 years ago

0 replies • 12753 views
Discussion

Disable Scan Shift Enable in Functional Mode

Category: Logic Design

By Terry2000
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updated over 12 years ago by bmiller

3 replies • 16177 views
Discussion

Multi Mode synthesis v/s Multi Corner synthesis

Category: Logic Design

By tanyacool
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started over 12 years ago

0 replies • 1572 views
Discussion

RTL Compiler Hierarchical Flow

Category: Logic Design

By lvcargnini
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updated over 12 years ago by grasshopper

1 replies • 13803 views
Discussion

Getting Error during Shadow logic insetion in share mode

Category: Logic Design

By ardas21
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started over 12 years ago

0 replies • 12787 views
Discussion

Lowpower : CPF Compiler support.

Category: Logic Design

By NTlp
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updated over 12 years ago by grasshopper

6 replies • 15656 views
Discussion

how preserve ports when use delete_unloaded_undriven command

Category: Logic Design

By daijin
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updated over 12 years ago by daijin

6 replies • 17527 views
Discussion

Vector File

Category: Logic Design

By girishmtech
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started over 12 years ago

0 replies • 13100 views
Discussion

Illegal assignment to constant

Category: Logic Design

By ardas21
•
started over 12 years ago

0 replies • 12855 views
Discussion

Conformal-LP : Understanding liberty files.

Category: Logic Design

By nitint08
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updated over 12 years ago by NTlp

6 replies • 19041 views
Discussion

RTL Complier flow with clock gating and scan insertion

Category: Logic Design

By Terry2000
•
updated over 12 years ago by Terry2000

2 replies • 15912 views
Discussion

Rtl Compiler behaviour on clock

Category: Logic Design

By tanyacool
•
updated over 12 years ago by grasshopper

3 replies • 13904 views

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