Logic Design

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Discussion

Scan mode and scan chain control from internal registers

Category: Logic Design

By Sinjeetp

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updated over 12 years ago by Sinjeetp

4 replies • 18144 views
Discussion

Exclude Paramter name/value during module generation in LEC

Category: Logic Design

By Rafeeq2129

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updated over 12 years ago by Rafeeq2129

2 replies • 2902 views
Discussion

Two warnings(external_delay and CSA rejected)

Category: Logic Design

By 20050710212

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updated over 12 years ago by grasshopper

1 replies • 1152 views
Discussion

module naming with hexadecimal values

Category: Logic Design

By Rafeeq2129

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updated over 12 years ago by tstark

2 replies • 15111 views
Discussion

Command to Store, Restore a RTL Compiler session

Category: Logic Design

By beginer

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updated over 12 years ago by grasshopper

3 replies • 17045 views
Discussion

RTL Compiler: VCD Annotation and CPF

Category: Logic Design

By moogydmaxim

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updated over 12 years ago by moogydmaxim

4 replies • 16362 views
Discussion

Verilog simulation using verilog XL

Category: Logic Design

By OLyonnais

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updated over 12 years ago by tstark

2 replies • 16895 views
Discussion

Error with Vendor-contributed Models in Simulation

Category: Logic Design

By sns22

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updated over 12 years ago by oldmouldy

1 replies • 14435 views
Discussion

ELC - Generic PDK 45 version 3.5 - Redefinition error

Category: Logic Design

By kmmankad

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started over 12 years ago

0 replies • 930 views
Discussion

Power Difference between Analog Simulation and RTL complier estimation

Category: Logic Design

By GreenGraphene

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updated over 12 years ago by Fotios Nt

1 replies • 14459 views
Discussion

Problem occurs when reading vcd in RTL Compiler

Category: Logic Design

By rexnyu

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updated over 12 years ago by rexnyu

5 replies • 18782 views
Discussion

Where is 7400.olb ?

Category: Logic Design

By ArealPerson

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updated over 12 years ago by oldmouldy

1 replies • 15066 views
Discussion

Error : Verilog-2001 feature.

Category: Logic Design

By rexnyu

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updated over 12 years ago by rexnyu

1 replies • 14828 views
Discussion

synthesis warning of undriven signal

Category: Logic Design

By projectd2007

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updated over 12 years ago by grasshopper

1 replies • 18474 views
Discussion

RC ; sdc ; load_of

Category: Logic Design

By Yemelya

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updated over 12 years ago by grasshopper

5 replies • 17804 views

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