Logic Design

Latest Posts

Discussion

Creating a reset scan test using Encounter Test

Category: Logic Design

By glennramalho
•
started over 13 years ago

0 replies • 14877 views
Discussion

set_false_path -through and set_load on the output ports

Category: Logic Design

By beginer
•
updated over 13 years ago by grasshopper

1 replies • 2675 views
Discussion

How do I delete clock groups (created via set_clock_groups)

Category: Logic Design

By moogydmaxim
•
updated over 13 years ago by grasshopper

1 replies • 16451 views
Discussion

How to use the Encounter RTL Compiler Super-Thread with Tivoli Workload LoadLeveler

Category: Logic Design

By lvcargnini
•
updated over 13 years ago by grasshopper

1 replies • 17261 views
Discussion

cell_leakage_power

Category: Logic Design

By msanyal
•
updated over 13 years ago by bmiller

1 replies • 15186 views
Discussion

Scan mode and scan chain control from internal registers

Category: Logic Design

By Sinjeetp
•
updated over 13 years ago by Sinjeetp

4 replies • 19569 views
Discussion

Exclude Paramter name/value during module generation in LEC

Category: Logic Design

By Rafeeq2129
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updated over 13 years ago by Rafeeq2129

2 replies • 3406 views
Discussion

Two warnings(external_delay and CSA rejected)

Category: Logic Design

By 20050710212
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updated over 13 years ago by grasshopper

1 replies • 1403 views
Discussion

module naming with hexadecimal values

Category: Logic Design

By Rafeeq2129
•
updated over 13 years ago by tstark

2 replies • 16026 views
Discussion

Command to Store, Restore a RTL Compiler session

Category: Logic Design

By beginer
•
updated over 13 years ago by grasshopper

3 replies • 18175 views
Discussion

RTL Compiler: VCD Annotation and CPF

Category: Logic Design

By moogydmaxim
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updated over 13 years ago by moogydmaxim

4 replies • 17571 views
Discussion

Verilog simulation using verilog XL

Category: Logic Design

By OLyonnais
•
updated over 13 years ago by tstark

2 replies • 17902 views
Discussion

Error with Vendor-contributed Models in Simulation

Category: Logic Design

By sns22
•
updated over 13 years ago by oldmouldy

1 replies • 15303 views
Discussion

ELC - Generic PDK 45 version 3.5 - Redefinition error

Category: Logic Design

By kmmankad
•
started over 13 years ago

0 replies • 1203 views
Discussion

Power Difference between Analog Simulation and RTL complier estimation

Category: Logic Design

By GreenGraphene
•
updated over 13 years ago by Fotios Nt

1 replies • 15330 views

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