Logic Design

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cell_leakage_power

Category: Logic Design

By msanyal
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updated over 13 years ago by bmiller

1 replies • 15030 views
Discussion

Scan mode and scan chain control from internal registers

Category: Logic Design

By Sinjeetp
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updated over 13 years ago by Sinjeetp

4 replies • 19052 views
Discussion

Exclude Paramter name/value during module generation in LEC

Category: Logic Design

By Rafeeq2129
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updated over 13 years ago by Rafeeq2129

2 replies • 3190 views
Discussion

Two warnings(external_delay and CSA rejected)

Category: Logic Design

By 20050710212
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updated over 13 years ago by grasshopper

1 replies • 1308 views
Discussion

module naming with hexadecimal values

Category: Logic Design

By Rafeeq2129
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updated over 13 years ago by tstark

2 replies • 15835 views
Discussion

Command to Store, Restore a RTL Compiler session

Category: Logic Design

By beginer
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updated over 13 years ago by grasshopper

3 replies • 17901 views
Discussion

RTL Compiler: VCD Annotation and CPF

Category: Logic Design

By moogydmaxim
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updated over 13 years ago by moogydmaxim

4 replies • 17181 views
Discussion

Verilog simulation using verilog XL

Category: Logic Design

By OLyonnais
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updated over 13 years ago by tstark

2 replies • 17664 views
Discussion

Error with Vendor-contributed Models in Simulation

Category: Logic Design

By sns22
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updated over 13 years ago by oldmouldy

1 replies • 15119 views
Discussion

ELC - Generic PDK 45 version 3.5 - Redefinition error

Category: Logic Design

By kmmankad
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started over 13 years ago

0 replies • 1080 views
Discussion

Power Difference between Analog Simulation and RTL complier estimation

Category: Logic Design

By GreenGraphene
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updated over 13 years ago by Fotios Nt

1 replies • 15152 views
Discussion

Problem occurs when reading vcd in RTL Compiler

Category: Logic Design

By rexnyu
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updated over 13 years ago by rexnyu

5 replies • 19814 views
Discussion

Where is 7400.olb ?

Category: Logic Design

By ArealPerson
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updated over 13 years ago by oldmouldy

1 replies • 15740 views
Discussion

Error : Verilog-2001 feature.

Category: Logic Design

By rexnyu
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updated over 13 years ago by rexnyu

1 replies • 15518 views
Discussion

synthesis warning of undriven signal

Category: Logic Design

By projectd2007
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updated over 13 years ago by grasshopper

1 replies • 19280 views

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