Logic Design

Latest Posts

Discussion

unwanted "\" in netlist

Category: Logic Design

By tompy
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updated over 13 years ago by tompy

2 replies • 2236 views
Discussion

The error of Synthesis

Category: Logic Design

By bravepanda
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started over 13 years ago

0 replies • 17601 views
Discussion

Question about the multiplier

Category: Logic Design

By bravepanda
•
updated over 13 years ago by grasshopper

3 replies • 18839 views
Discussion

Library requirements during elaboration stage

Category: Logic Design

By tanyacool
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updated over 13 years ago by tanyacool

2 replies • 16046 views
Discussion

how to define scan chains in RC

Category: Logic Design

By tanyacool
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updated over 13 years ago by grasshopper

1 replies • 17651 views
Discussion

Include a IP netlist during Synthesis of a complete design

Category: Logic Design

By Bapaiah
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updated over 13 years ago by Bapaiah

2 replies • 15509 views
Discussion

RC - read_hdl

Category: Logic Design

By Yemelya
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updated over 13 years ago by Yemelya

2 replies • 6161 views
Discussion

Does clock power included in Power Report ?

Category: Logic Design

By dkhan
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updated over 13 years ago by dkhan

2 replies • 17600 views
Discussion

power differences after post-syn using VCD

Category: Logic Design

By leez2006
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updated over 13 years ago by leez2006

2 replies • 16963 views
Discussion

how to add synthesizable delay in design

Category: Logic Design

By yasir khan
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updated over 13 years ago by Paul Bibin

1 replies • 16552 views
Discussion

How to avoid unwanted removal of logic during synthesis

Category: Logic Design

By dkhan
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updated over 13 years ago by dkhan

2 replies • 21067 views
Discussion

RTL compiler command for retaining design hierarchy

Category: Logic Design

By dkhan
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updated over 13 years ago by dkhan

2 replies • 18711 views
Discussion

how to compare designware like DW02_multp with LEC

Category: Logic Design

By codefire
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updated over 13 years ago by conformalfan

3 replies • 17192 views
Discussion

Conformal LEC Dofile Arguments.

Category: Logic Design

By scrip
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updated over 13 years ago by tstark

3 replies • 19973 views
Discussion

RTL compiler to minimize area

Category: Logic Design

By Hamzah
•
updated over 13 years ago by Hamzah

4 replies • 21356 views

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