Logic Design

Latest Posts

Discussion

how to define scan chains in RC

Category: Logic Design

By tanyacool
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updated over 12 years ago by grasshopper

1 replies • 17423 views
Discussion

Include a IP netlist during Synthesis of a complete design

Category: Logic Design

By Bapaiah
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updated over 12 years ago by Bapaiah

2 replies • 15347 views
Discussion

RC - read_hdl

Category: Logic Design

By Yemelya
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updated over 12 years ago by Yemelya

2 replies • 5779 views
Discussion

Does clock power included in Power Report ?

Category: Logic Design

By dkhan
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updated over 12 years ago by dkhan

2 replies • 17338 views
Discussion

power differences after post-syn using VCD

Category: Logic Design

By leez2006
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updated over 12 years ago by leez2006

2 replies • 16720 views
Discussion

how to add synthesizable delay in design

Category: Logic Design

By yasir khan
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updated over 12 years ago by Paul Bibin

1 replies • 16414 views
Discussion

How to avoid unwanted removal of logic during synthesis

Category: Logic Design

By dkhan
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updated over 12 years ago by dkhan

2 replies • 20616 views
Discussion

RTL compiler command for retaining design hierarchy

Category: Logic Design

By dkhan
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updated over 12 years ago by dkhan

2 replies • 18513 views
Discussion

how to compare designware like DW02_multp with LEC

Category: Logic Design

By codefire
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updated over 12 years ago by conformalfan

3 replies • 16958 views
Discussion

Conformal LEC Dofile Arguments.

Category: Logic Design

By scrip
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updated over 12 years ago by tstark

3 replies • 19659 views
Discussion

RTL compiler to minimize area

Category: Logic Design

By Hamzah
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updated over 12 years ago by Hamzah

4 replies • 20632 views
Discussion

Creating a reset scan test using Encounter Test

Category: Logic Design

By glennramalho
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started over 12 years ago

0 replies • 14774 views
Discussion

set_false_path -through and set_load on the output ports

Category: Logic Design

By beginer
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updated over 13 years ago by grasshopper

1 replies • 2531 views
Discussion

How do I delete clock groups (created via set_clock_groups)

Category: Logic Design

By moogydmaxim
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updated over 13 years ago by grasshopper

1 replies • 16170 views
Discussion

How to use the Encounter RTL Compiler Super-Thread with Tivoli Workload LoadLeveler

Category: Logic Design

By lvcargnini
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updated over 13 years ago by grasshopper

1 replies • 17090 views

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