Logic Design

Latest Posts

Discussion

Conformal- LEC

Category: Logic Design

By Indira S
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updated over 12 years ago by tstark

1 replies • 3085 views
Discussion

Algorithm used for implementation of Division

Category: Logic Design

By S0MA
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updated over 12 years ago by S0MA

2 replies • 16570 views
Discussion

Instance name mismatch between .v and .sdf writen from RTL compiler

Category: Logic Design

By zczc999
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started over 12 years ago

0 replies • 15455 views
Discussion

Preserving structure in RTL Compiler

Category: Logic Design

By Aram Shahinyan
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updated over 12 years ago by grasshopper

7 replies • 22379 views
Discussion

CIS Schematic Page numbering

Category: Logic Design

By budnoel
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started over 12 years ago

0 replies • 14607 views
Discussion

How to set_current_module in RTL Compiler??

Category: Logic Design

By archive
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updated over 12 years ago by jojo57006

10 replies • 21178 views
Discussion

re-target technology node

Category: Logic Design

By DDEOTA
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started over 12 years ago

0 replies • 14382 views
Discussion

Force RTL compiler not to optimize certain part of the design

Category: Logic Design

By rexnyu
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updated over 12 years ago by grasshopper

1 replies • 17255 views
Discussion

What is 'comment' character for ihdl files?

Category: Logic Design

By sayn
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started over 12 years ago

0 replies • 5673 views
Discussion

where can we get the RAK

Category: Logic Design

By tanyacool
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updated over 12 years ago by Azar990

2 replies • 17621 views
Discussion

Asynchronous FIFO design

Category: Logic Design

By abhinavpr
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updated over 12 years ago by KennyWylies

7 replies • 24725 views
Discussion

where can i get gate.lib

Category: Logic Design

By Anasios
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updated over 13 years ago by oldmouldy

1 replies • 17277 views
Discussion

RC: set_min/max_delay breaks the constrained paths

Category: Logic Design

By Sporadic Crash
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updated over 13 years ago by sjoshi

3 replies • 5331 views
Discussion

What does Constant hierarchical Pin(s) means in RTL compiler?

Category: Logic Design

By Bardia B
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updated over 13 years ago by bmiller

1 replies • 9108 views
Discussion

*E,TRFILEIO: file I/O Error using textio.all library in Sigasi

Category: Logic Design

By melisanthi
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started over 13 years ago

0 replies • 1583 views

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