Logic Design

Latest Posts

Discussion

how preserve ports when use delete_unloaded_undriven command

Category: Logic Design

By daijin
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updated over 13 years ago by daijin

6 replies • 20851 views
Discussion

Vector File

Category: Logic Design

By girishmtech
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started over 13 years ago

0 replies • 14827 views
Discussion

Illegal assignment to constant

Category: Logic Design

By ardas21
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started over 13 years ago

0 replies • 14618 views
Discussion

Conformal-LP : Understanding liberty files.

Category: Logic Design

By nitint08
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updated over 13 years ago by NTlp

6 replies • 23187 views
Discussion

RTL Complier flow with clock gating and scan insertion

Category: Logic Design

By Terry2000
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updated over 13 years ago by Terry2000

2 replies • 19286 views
Discussion

Rtl Compiler behaviour on clock

Category: Logic Design

By tanyacool
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updated over 13 years ago by grasshopper

3 replies • 16125 views
Discussion

no constraints on hierarchial boundaries

Category: Logic Design

By tanyacool
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updated over 13 years ago by grasshopper

1 replies • 14938 views
Discussion

How do we exclued delay cells in RC

Category: Logic Design

By tanyacool
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updated over 13 years ago by grasshopper

1 replies • 15026 views
Discussion

Conformal-LP : CPF_LIB1 not flagging.

Category: Logic Design

By nitint08
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updated over 13 years ago by tstark

1 replies • 15309 views
Discussion

Conformal LP : Merging CPF files.

Category: Logic Design

By nitint08
•
updated over 13 years ago by tstark

1 replies • 15073 views
Discussion

difference between Random Resistance faults and deterministic faults?

Category: Logic Design

By vipul982
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updated over 13 years ago by bmiller

1 replies • 17593 views
Discussion

How do I insert test point in the model?

Category: Logic Design

By vipul982
•
started over 13 years ago

0 replies • 14661 views
Discussion

test procedure in Cadence encounter test tool?

Category: Logic Design

By vipul982
•
updated over 13 years ago by vipul982

4 replies • 18103 views
Discussion

Does test compaction reduces tester time or memory or both?

Category: Logic Design

By vipul982
•
updated over 13 years ago by vipul982

2 replies • 15755 views
Discussion

how to connect multi clock domians to only one scan chain

Category: Logic Design

By MoKhairy
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updated over 13 years ago by bmiller

1 replies • 17312 views

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