Logic Design

Latest Posts

Discussion

RTL Complier flow with clock gating and scan insertion

Category: Logic Design

By Terry2000
•
updated over 13 years ago by Terry2000

2 replies • 18626 views
Discussion

Rtl Compiler behaviour on clock

Category: Logic Design

By tanyacool
•
updated over 13 years ago by grasshopper

3 replies • 15917 views
Discussion

no constraints on hierarchial boundaries

Category: Logic Design

By tanyacool
•
updated over 13 years ago by grasshopper

1 replies • 14793 views
Discussion

How do we exclued delay cells in RC

Category: Logic Design

By tanyacool
•
updated over 13 years ago by grasshopper

1 replies • 14887 views
Discussion

Conformal-LP : CPF_LIB1 not flagging.

Category: Logic Design

By nitint08
•
updated over 13 years ago by tstark

1 replies • 15153 views
Discussion

Conformal LP : Merging CPF files.

Category: Logic Design

By nitint08
•
updated over 13 years ago by tstark

1 replies • 14917 views
Discussion

difference between Random Resistance faults and deterministic faults?

Category: Logic Design

By vipul982
•
updated over 13 years ago by bmiller

1 replies • 17286 views
Discussion

How do I insert test point in the model?

Category: Logic Design

By vipul982
•
started over 13 years ago

0 replies • 14581 views
Discussion

test procedure in Cadence encounter test tool?

Category: Logic Design

By vipul982
•
updated over 13 years ago by vipul982

4 replies • 17814 views
Discussion

Does test compaction reduces tester time or memory or both?

Category: Logic Design

By vipul982
•
updated over 13 years ago by vipul982

2 replies • 15577 views
Discussion

how to connect multi clock domians to only one scan chain

Category: Logic Design

By MoKhairy
•
updated over 13 years ago by bmiller

1 replies • 16977 views
Discussion

dft settings during DFT scan insertion

Category: Logic Design

By tanyacool
•
updated over 13 years ago by nannasin28

4 replies • 21217 views
Discussion

Reg .VCD file generation

Category: Logic Design

By Music
•
updated over 13 years ago by nannasin28

8 replies • 24615 views
Discussion

How to handle pre defined generated clocks in .libs.

Category: Logic Design

By sureshm
•
started over 13 years ago

0 replies • 16218 views
Discussion

MBIST insertion using RC tool

Category: Logic Design

By Srikanth Y
•
updated over 13 years ago by Srikanth Y

2 replies • 16702 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.