Logic Design

Latest Posts

Discussion

dft settings during DFT scan insertion

Category: Logic Design

By tanyacool
•
updated over 13 years ago by nannasin28

4 replies • 21941 views
Discussion

Reg .VCD file generation

Category: Logic Design

By Music
•
updated over 13 years ago by nannasin28

8 replies • 25247 views
Discussion

How to handle pre defined generated clocks in .libs.

Category: Logic Design

By sureshm
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started over 13 years ago

0 replies • 16431 views
Discussion

MBIST insertion using RC tool

Category: Logic Design

By Srikanth Y
•
updated over 13 years ago by Srikanth Y

2 replies • 16875 views
Discussion

Need help on forward body biasing and CSAFF&CHLFF circuit

Category: Logic Design

By ntus
•
started over 13 years ago

0 replies • 871 views
Discussion

How to give a bit string as input in cadence virtuose spectre?

Category: Logic Design

By bsddsb
•
started over 13 years ago

0 replies • 15206 views
Discussion

Trouble with reading vcd file in RC 11.2

Category: Logic Design

By Chongxi
•
updated over 13 years ago by grasshopper

1 replies • 15092 views
Discussion

RTL Compiler, Min Libraries and CPF

Category: Logic Design

By moogyd
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updated over 13 years ago by grasshopper

3 replies • 16975 views
Discussion

Synthesis in rclabs using slow and fast library

Category: Logic Design

By Maheshnb
•
updated over 13 years ago by grasshopper

3 replies • 17945 views
Discussion

How to add Synthesizable delay into the module

Category: Logic Design

By Maheshnb
•
updated over 13 years ago by grasshopper

1 replies • 15074 views
Discussion

max_fanout constraint

Category: Logic Design

By tanyacool
•
started over 13 years ago

0 replies • 14926 views
Discussion

how to find out the FFs connected to the output of a selected FF

Category: Logic Design

By gops
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updated over 13 years ago by bmiller

1 replies • 14950 views
Discussion

what dose pulse width mean in timing report

Category: Logic Design

By small5
•
started over 13 years ago

0 replies • 14945 views
Discussion

RTL Compiler synthesis commands for TDC design

Category: Logic Design

By Maheshnb
•
started over 13 years ago

0 replies • 14925 views
Discussion

RC: to Remove PG pins from a Netlist..

Category: Logic Design

By Yemelya
•
updated over 14 years ago by bmiller

1 replies • 16806 views

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