Logic Design

Latest Posts

Discussion

-binding flag is ignored by ncelab

Category: Logic Design

By myonlyscreen
•
updated over 13 years ago by TAM1

3 replies • 3830 views
Discussion

area calculation by RC

Category: Logic Design

By tanyacool
•
updated over 13 years ago by bmiller

1 replies • 15383 views
Discussion

Should I bother about the PLL delay?

Category: Logic Design

By gops
•
updated over 13 years ago by grasshopper

2 replies • 15667 views
Discussion

RTL Compiler tutorial

Category: Logic Design

By ubbala
•
updated over 13 years ago by grasshopper

1 replies • 15080 views
Discussion

How to Simulate 64-bit VHDL Code in Cadence?

Category: Logic Design

By shahein
•
started over 13 years ago

0 replies • 14572 views
Discussion

LEC report additional FF

Category: Logic Design

By theodoredj
•
updated over 13 years ago by affaqq

7 replies • 21578 views
Discussion

LEC and Designware components

Category: Logic Design

By jlang
•
updated over 13 years ago by affaqq

1 replies • 15624 views
Discussion

how to map a particular library cell to a component

Category: Logic Design

By gops
•
updated over 13 years ago by renobreint

1 replies • 15350 views
Discussion

CDC Functional Checks taking too much time.

Category: Logic Design

By arunvaidya
•
updated over 13 years ago by arunvaidya

3 replies • 16044 views
Discussion

RTL Compiler: DFT Checks and non controllable/observable I/O

Category: Logic Design

By moogyd
•
updated over 13 years ago by moogyd

6 replies • 5078 views
Discussion

Standard Cell Library Design

Category: Logic Design

By pmuppala
•
updated over 13 years ago by gentle

1 replies • 15728 views
Discussion

dsn-files

Category: Logic Design

By wschira
•
started over 13 years ago

0 replies • 14870 views
Discussion

.so cell import ?

Category: Logic Design

By DavidRo
•
started over 13 years ago

0 replies • 14238 views
Discussion

RC-compiler Error create isolation rule and retention rule failed.....

Category: Logic Design

By yasir khan
•
started over 13 years ago

0 replies • 14508 views
Discussion

CPF_Read Issue

Category: Logic Design

By affaqq
•
updated over 13 years ago by tstark

2 replies • 15312 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.