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Logic Design

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  • Discussion

    RC-compiler Error create isolation rule and retention rule failed.....

    Category: Logic Design

    By yasir khan

    •

    started over 14 years ago

    0 replies • 14578 views
  • Discussion

    CPF_Read Issue

    Category: Logic Design

    By affaqq

    •

    updated over 14 years ago by tstark

    2 replies • 15418 views
  • Discussion

    clock tree design

    Category: Logic Design

    By cupidsd

    •

    started over 14 years ago

    0 replies • 14488 views
  • Discussion

    How to see power trace

    Category: Logic Design

    By ganeshK2012

    •

    started over 14 years ago

    0 replies • 14795 views
  • Discussion

    Difference Between PLE, Spatial, Physical

    Category: Logic Design

    By sureshm

    •

    updated over 14 years ago by grasshopper

    1 replies • 21270 views
  • Discussion

    Any comments on the RC Physical Timing co-relation with EDI?

    Category: Logic Design

    By sureshm

    •

    updated over 14 years ago by grasshopper

    1 replies • 15061 views
  • Discussion

    Simulating verilog using cadence

    Category: Logic Design

    By MTP3

    •

    updated over 14 years ago by MTP3

    1 replies • 15330 views
  • Discussion

    Regarding retiming....which license is required

    Category: Logic Design

    By ChInNi miSSing

    •

    updated over 14 years ago by mclarke

    1 replies • 15023 views
  • Discussion

    Check out Conformal documentation via its web interface!

    Category: Logic Design

    By hummingbird

    •

    updated over 14 years ago by tstark

    1 replies • 15679 views
  • Discussion

    Why boundary_opto cause to LEC fail?

    Category: Logic Design

    By PengpengHao

    •

    updated over 14 years ago by tstark

    1 replies • 15268 views
  • Discussion

    Propagate a clock from .LIB of a block

    Category: Logic Design

    By randomax

    •

    started over 14 years ago

    0 replies • 14798 views
  • Discussion

    How to synthesize without scan cell replacement

    Category: Logic Design

    By Maso

    •

    updated over 14 years ago by Maso

    7 replies • 26756 views
  • Discussion

    Checking equivalence of buffer trees

    Category: Logic Design

    By BufferTree

    •

    updated over 14 years ago by tstark

    1 replies • 16378 views
  • Discussion

    How to calculate speed for each path_group in RTL Compiler

    Category: Logic Design

    By Maso

    •

    updated over 14 years ago by Maso

    2 replies • 15337 views
  • Discussion

    How can I remove module before writing whole netlist out

    Category: Logic Design

    By Maso

    •

    updated over 14 years ago by Maso

    2 replies • 15860 views
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