• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design & IC Packaging (Allegro X)

PCB Design & IC Packaging (Allegro X)

CDNS Forum PCB Categories

Allegro X PCB Editor

Allegro X Capture CIS

Allegro X System Capture (EE Cockpit)

Allegro X Pulse & EDM

Allegro X APD

Allegro X Scripting - Skill

Allegro X Scripting - TCL

PCB Design Archive

Design Entry HDL

PSpice

Licensing & Installation

  • Leaderboard

    PCB Design

    • 1
      excellon1
      excellon1 30 Points
    • 2
      steve
      steve 25 Points
    • 3
      Ejlersen
      Ejlersen 20 Points
    • 3
      Robert Finley
      Robert Finley 20 Points
    • 5
      HirokiJEM
      HirokiJEM 16 Points
  • Leaderboard

    PCB Design

    • 1
      steve
      steve 15,903 Points
    • 2
      oldmouldy
      oldmouldy 11,035 Points
    • 3
      eDave
      eDave 7,651 Points
    • 4
      DavidJHutchins
      DavidJHutchins 5,226 Points
    • 5
      redwire
      redwire 5,193 Points

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List

Latest Posts

  • Discussion

    how to import virtuoso gds output in to APD (advanced package designer)

    Category: Allegro X APD

    By archive

    •

    updated over 18 years ago by archive

    7 replies • 20835 views
  • Discussion

    How to hilight nets or symbols

    Category: Allegro X PCB Editor

    By archive

    •

    started over 18 years ago

    0 replies • 12760 views
  • Discussion

    extracta command line for - Etch Length by Pin Pair

    Category: Allegro X PCB Editor

    By archive

    •

    started over 18 years ago

    0 replies • 1176 views
  • Discussion

    warning: "could not fit symbol"

    Category: PCB Design

    By archive

    •

    updated over 18 years ago by archive

    3 replies • 3257 views
  • Discussion

    Allegro Padstacks; Defined Geometry vs. Flash

    Category: PCB Design

    By archive

    •

    updated over 18 years ago by archive

    3 replies • 15188 views
  • Discussion

    About Design Attributes

    Category: Allegro X PCB Editor

    By archive

    •

    updated over 18 years ago by archive

    1 replies • 13460 views
  • Discussion

    Using .sp file for connector in SigXP

    Category: PCB Design

    By archive

    •

    updated over 18 years ago by archive

    4 replies • 14970 views
  • Discussion

    Orcad Post Processing Layer Limitations

    Category: PCB Design

    By archive

    •

    started over 18 years ago

    0 replies • 12766 views
  • Discussion

    Dynamic copper fill problem

    Category: PCB Design

    By archive

    •

    updated over 18 years ago by archive

    8 replies • 20110 views
  • Discussion

    Wrong assembly plan on Orcad 10.5

    Category: PCB Design

    By archive

    •

    started over 18 years ago

    0 replies • 12744 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information