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PCB Design & IC Packaging (Allegro X)

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Forum - Thread List

Latest Posts

  • Answered

    Errors in 3D canvas when Via size is less than 100um

    Category: Allegro X APD

    By YY20241209613

    •

    updated 8 months ago by mahimag

    3 replies • 3601 views
  • Discussion

    PSpice for TI Simulation Running Very Slow

    Category: PSpice

    By JM202503166347

    •

    updated 8 months ago by rg13

    1 replies • 1468 views
  • Suggested Answer

    Design Entry HDL error spcocd-152

    Category: Design Entry HDL

    By VC202503176623

    •

    updated 8 months ago by rg13

    1 replies • 1549 views
  • Discussion

    Net Connectivity: Share Your Insights

    Category: Allegro X Capture CIS

    By PCBTech

    •

    updated 8 months ago by PCBTech

    6 replies • 1291 views
  • Discussion

    SysCap – Tip of the Week: Allegro System Capture in Offline Mode

    Category: Allegro X System Capture (EE Cockpit)

    By DesignTech

    •

    updated 9 months ago by elsewhereflat

    1 replies • 3507 views
  • Not Answered

    Capture Part Manager Questions

    Category: Allegro X Capture CIS

    By Adam

    •

    updated 9 months ago by Adam

    2 replies • 924 views
  • Answered

    Differential Signal symbol

    Category: Allegro X Capture CIS

    By KD202502275710

    •

    updated 9 months ago by KD202502275710

    6 replies • 1880 views
  • Answered

    Cloud Network - Cadence

    Category: Allegro X Capture CIS

    By KD202502275710

    •

    updated 9 months ago by KD202502275710

    4 replies • 1129 views
  • Suggested Answer

    How can I void multiple static shapes (like 500 or so) with 1 shape?

    Category: Allegro X PCB Editor

    By AN202503141654

    •

    updated 9 months ago by excellon1

    1 replies • 2300 views
  • Answered

    auto routing working time

    Category: Allegro X PCB Editor

    By JJ202503101021

    •

    updated 9 months ago by Robert Finley

    3 replies • 2837 views
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