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  • Discussion

    When the net schedule is set in the PCB editor and auto-routing is executed, the routing is different from the set schedule. Locked

    12756 views
    3 replies
    Latest over 5 years ago
    by steve
  • Discussion

    WARNING(ORNET-1119): The part/device cannot be simulated. No PSpiceTemplate found on J1, ignoring this part/device from simulation netlist Locked

    7818 views
    1 reply
    Latest over 5 years ago
    by desertbird
  • Discussion

    Via Overlapp

    11471 views
    0 replies
    Started over 5 years ago
    by vimaldevlpr
  • Discussion

    How to do "arbitrary" measurement between 2 points / components

    1665 views
    0 replies
    Started over 5 years ago
    by U00000000
  • Discussion

    Hotkey, funckey or skill

    7426 views
    0 replies
    Started over 5 years ago
    by mgallman1
  • Discussion

    How to zoom fit screen by axl command

    13077 views
    2 replies
    Latest over 5 years ago
    by Hunterdr
  • Discussion

    How to solve the via shorting issue? Locked

    13366 views
    3 replies
    Latest over 5 years ago
    by Lock2002
  • Discussion

    Exporting Libraries

    12299 views
    2 replies
    Latest over 5 years ago
    by vimaldevlpr
  • Discussion

    Cant create netlist in capture cis Locked

    12729 views
    3 replies
    Latest over 5 years ago
    by Alok Tripathi
  • Discussion

    Allegro Design Entry HDL: Script to arrange and make defined property visible

    12038 views
    0 replies
    Started over 5 years ago
    by Sreejesh Rajesh
  • Discussion

    can't route differential net Locked

    2432 views
    3 replies
    Latest over 5 years ago
    by AvengerThanos
  • Discussion

    difference between the 4 layer & 6 layer Locked

    2267 views
    1 reply
    Latest over 5 years ago
    by AvengerThanos
  • Discussion

    how many CPU cores can use for Allegro PCB Editor maximally? Locked

    13334 views
    1 reply
    Latest over 5 years ago
    by AvengerThanos
  • Discussion

    Hi, could you please tell me how to clear or delete the DRC constrain setting as shown below. Thanks Locked

    13709 views
    3 replies
    Latest over 5 years ago
    by AvengerThanos
  • Discussion

    STEP file generation Locked

    17437 views
    3 replies
    Latest over 5 years ago
    by AvengerThanos
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