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Discussion

Testprep Automatic - allow pin escape insertion function - doesn't work as expected Locked

1548 views

1 reply

Latest over 6 years ago
by AleksMK
Discussion

why line to SMD Pin same net spacing DRC？they are one the same net. Locked

2905 views

3 replies

Latest over 6 years ago
by johnthanchau
Discussion

DRC ERROR Locked

13518 views

1 reply

Latest over 6 years ago
by steve
Discussion

offsetting a void shape Locked

12938 views

0 replies

Started over 6 years ago
by masamasa
Discussion

Refresh Capture.ini without restarting Capture? Locked

13793 views

0 replies

Started over 6 years ago
by aricbeaver
Discussion

Bend operations disabled due to licensing and/or DLL installation issues Locked

1488 views

2 replies

Latest over 6 years ago
by willbi
Discussion

Allegro 17.2: Logo Creation Locked

18901 views

7 replies

Latest over 6 years ago
by eDave
Discussion

Creating an alternate sch symbol for a multi piece component allegro HDL 17.2 Locked

13122 views

0 replies

Started over 6 years ago
by CharlesP
Discussion

[Capture CIS] Preview 3D model for database parts + more component details Locked

17049 views

6 replies

Latest over 6 years ago
by Mysil B
Discussion

Creating paste stencil with both sides in one stencil Locked

13571 views

0 replies

Started over 6 years ago
by CSCNalu
Discussion

micro-via to buried via spacing Locked

15760 views

3 replies

Latest over 6 years ago
by Lock2002
Discussion

OrCad PCB Editor File Extensions - a definitive list *please* Locked

21001 views

5 replies

Latest over 6 years ago
by Mysil B
Discussion

Setting DC impedance for nets Locked

16580 views

7 replies

Latest over 6 years ago
by Mysil B
Discussion

select entire net refresh in 17.2HF052 capture is very slow Locked

18813 views

10 replies

Latest over 6 years ago
by LouShay
Discussion

Highlight all Untested nets simultaneously? Locked

14443 views

4 replies

Latest over 6 years ago
by JFuoco

Testprep Automatic - allow pin escape insertion function - doesn't work as expected Locked

why line to SMD Pin same net spacing DRC？they are one the same net. Locked

DRC ERROR Locked

offsetting a void shape Locked

Refresh Capture.ini without restarting Capture? Locked

Bend operations disabled due to licensing and/or DLL installation issues Locked

Allegro 17.2: Logo Creation Locked

Creating an alternate sch symbol for a multi piece component allegro HDL 17.2 Locked

[Capture CIS] Preview 3D model for database parts + more component details Locked

Creating paste stencil with both sides in one stencil Locked

micro-via to buried via spacing Locked

OrCad PCB Editor File Extensions - a definitive list *please* Locked

Setting DC impedance for nets Locked

select entire net refresh in 17.2HF052 capture is very slow Locked

Highlight all Untested nets simultaneously? Locked

OrCad PCB Editor File Extensions - a definitive list please Locked