• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  • Site
  • Community Search
  • User
Forum - Thread List
  • Suggested Answer

    How to get a report showing padstack (and shapes used in it) library path ? 0

    6372 views
    8 replies
    Latest 23 days ago
    by steve
  • Not Answered

    Generate ORCAD netlist (with orWirelist.dll) using TCL Script 0

    5179 views
    2 replies
    Latest 23 days ago
    by TechnoBobby
  • Answered

    customized GUI to control artwork film 0

    506 views
    2 replies
    Latest 23 days ago
    by MZ20250602835
  • Discussion

    Tip: Visualizing spacing net classes using Class Color

    140 views
    0 replies
    Started 24 days ago
    by Gowtham P
  • Not Answered

    Seeing true Values in CIS explorer , 0

    503 views
    5 replies
    Latest 24 days ago
    by Mhawley1
  • Not Answered

    How to close the preview when print a pdf in orcad 17.4 0

    552 views
    5 replies
    Latest 24 days ago
    by Jeet
  • Not Answered

    Exclude description while update part status 0

    411 views
    1 reply
    Latest 26 days ago
    by Jeet
  • Discussion

    Exploring Advanced Packaging: 2.5D vs. 3D

    2025 views
    2 replies
    Latest 26 days ago
    by JV202605125312
  • Discussion

    How to start SKILL IDE from APD or Allegro in Linux?

    203 views
    0 replies
    Started 27 days ago
    by JuanCR
  • Discussion

    Tip: Smooth Your Clines Without Breaking Phase Tuning

    1209 views
    3 replies
    Latest 27 days ago
    by avant
  • Not Answered

    Autorouter Help in APD 24.1 0

    255 views
    1 reply
    Latest 27 days ago
    by SaiPavanl
  • Not Answered

    Exporting PSPICE netlist with Subckt parameters 0

    368 views
    4 replies
    Latest 28 days ago
    by oldmouldy
  • Not Answered

    Sneak circuit analysis 0

    372 views
    2 replies
    Latest 28 days ago
    by Shashank
  • Not Answered

    Persistent netlisting error 0

    266 views
    1 reply
    Latest 28 days ago
    by IshaS
  • Discussion

    Simplify Schematic Management with Function Overlays in System Capture

    132 views
    0 replies
    Started 29 days ago
    by Akshay khosla
<>

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information