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    Generating S-parameters 8-port Sch from netlist Locked

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    by Quek
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    Problem with Pcell and its CDF Locked

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    Latest over 15 years ago
    by Renee
  • Discussion

    LVS error Locked

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    4 replies
    Latest over 15 years ago
    by Quek
  • Discussion

    Design Entry HDL_Library Locked

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    1 reply
    Latest over 15 years ago
    by erivas
  • Discussion

    Unique DIFFERENTIAL_PAIR properties on complex hierarchical designs : ConceptHDL Locked

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    Started over 15 years ago
    by aredenbaugh
  • Discussion

    sync corners tool output with ADE outputs Locked

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    7 replies
    Latest over 15 years ago
    by Andrew Beckett
  • Discussion

    Auto rename refdes problem - v16.3 Locked

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    1 reply
    Latest over 15 years ago
    by redwire
  • Discussion

    Virtuoso Corners Analysis SKILL commands Locked

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    1 reply
    Latest over 15 years ago
    by Andrew Beckett
  • Discussion

    error name too long Locked

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    3 replies
    Latest over 15 years ago
    by dumarjo
  • Discussion

    vbit source in analogLib Locked

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    1 reply
    Latest over 15 years ago
    by Andrew Beckett
  • Discussion

    Running Voltagestorm from Encounter Locked

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    4 replies
    Latest over 15 years ago
    by mariuse
  • Discussion

    placing pin in bottom layer Locked

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    2 replies
    Latest over 15 years ago
    by anandaraj
  • Discussion

    Relocating an Established Datum Locked

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    4 replies
    Latest over 15 years ago
    by Goblin60
  • Discussion

    Symbol creation in design entry hdl Locked

    13549 views
    0 replies
    Started over 15 years ago
    by Neha Anu
  • Discussion

    NCVHDL Compiler Locked

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    0 replies
    Started over 15 years ago
    by wolf82
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