• Discussion

  Does reset requires a tree structure like clock? Locked

  16156 views
  3 replies
  Latest over 16 years ago
  by Kari
• Discussion

  displaying units on PCB-16.2 Locked

  14488 views
  6 replies
  Latest over 16 years ago
  by redwire
• Discussion

  Propagated clocks Locked

  18424 views
  3 replies
  Latest over 16 years ago
  by grasshopper
• Discussion

  Assura 3.1 Error -VDB- Locked

  2059 views
  4 replies
  Latest over 16 years ago
  by Andrew Beckett
• Discussion

  OVM: Unable to change objects default configuration Locked

  14067 views
  2 replies
  Latest over 16 years ago
  by JanP
• Discussion

  Cadence Skill - Totally Buggy? Locked

  2634 views
  5 replies
  Latest over 16 years ago
  by Andrew Beckett
• Discussion

  ocean read data from 2 simulation directories in 6.1.3 Locked

  14827 views
  5 replies
  Latest over 16 years ago
  by jingguang
• Discussion

  Autorouting in Allegro PCB editor(Allegro PCB design GXL V16.0) Locked

  721 views
  1 reply
  Latest over 16 years ago
  by redwire
• Discussion

  Filtering of false DRC violations due to routing blockages in enounter. Locked

  14008 views
  1 reply
  Latest over 16 years ago
  by BobD
• Discussion

  Problem in using v2lvs to convert verilog netlist into spice netlist Locked

  20284 views
  2 replies
  Latest over 16 years ago
  by rh0dium
• Discussion

  Set Constraints for Specific Region Locked

  13311 views
  3 replies
  Latest over 16 years ago
  by Tanveer
• Discussion

  Autorouting with do file Locked

  12889 views
  0 replies
  Started over 16 years ago
  by Neha Anu
• Discussion

  Is it possible to write out a wireload model from encounter? Locked

  14139 views
  3 replies
  Latest over 16 years ago
  by gops
• Discussion

  Fix error in schematic HDL Locked

  18723 views
  7 replies
  Latest over 16 years ago
  by ELEKVN
• Discussion

  Time average transient waveforms??? Locked

  17687 views
  1 reply
  Latest over 16 years ago
  by markbeck