• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    Can OpenAccess stream in abd out gzip gds Locked

    13835 views
    1 reply
    Latest over 16 years ago
    by Andrew Beckett
  • Discussion

    How to programtically rename a selected pin Locked

    18097 views
    4 replies
    Latest over 16 years ago
    by Andrew Beckett
  • Discussion

    Cut Guard Ring - Turbo box function Locked

    585 views
    0 replies
    Started over 16 years ago
    by kashvi
  • Discussion

    Continue_error Locked

    14067 views
    3 replies
    Latest over 16 years ago
    by MVSI
  • Discussion

    Is there anything like custom IC design skill function "hiGetWindows"???

    668 views
    1 reply
    Latest over 16 years ago
    by eDave
  • Discussion

    Modify Module Locked

    12855 views
    1 reply
    Latest over 16 years ago
    by Khurana
  • Discussion

    Menu File Documentation? Locked

    14690 views
    7 replies
    Latest over 16 years ago
    by wilef
  • Discussion

    Routing pin pairs on the same net as a differential pair Locked

    12811 views
    0 replies
    Started over 16 years ago
    by kFactor
  • Discussion

    Unresolved adater ERR_DID_NOT_FIND_ADAPTER Locked

    14174 views
    2 replies
    Latest over 16 years ago
    by random
  • Discussion

    Simulation Problem : resolving X of a un-initialized f/f whose output feedback to itself thru some logic Locked

    2946 views
    1 reply
    Latest over 16 years ago
    by StephenH
  • Discussion

    test to write and read registers with field order like packing.low Locked

    13535 views
    1 reply
    Latest over 16 years ago
    by StephenH
  • Discussion

    VHDL2001 import to cadence (protected type) Locked

    13661 views
    1 reply
    Latest over 16 years ago
    by Andrew Beckett
  • Discussion

    Optimal (fast) callback for pcells Locked

    14763 views
    3 replies
    Latest over 16 years ago
    by Andrew Beckett
  • Discussion

    Layout and LVS of a non-standard device! Locked

    15774 views
    3 replies
    Latest over 16 years ago
    by Andrew Beckett
  • Discussion

    Verilog, System Verilog and SystemC Locked

    18195 views
    3 replies
    Latest over 16 years ago
    by mstellfox
<>

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information