• Discussion

  Controlling the length of a wire for which it has to be taperred in width. Locked

  13904 views
  3 replies
  Latest over 16 years ago
  by Kari
• Discussion

  length matching across groups of nets Locked

  14283 views
  3 replies
  Latest over 16 years ago
  by Dennis Nagle
• Discussion

  Incorrect Fractional Cell Error Locked

  13846 views
  2 replies
  Latest over 16 years ago
  by danielmo
• Discussion

  IC-PKG Co-design Webinar Aug 26

  12863 views
  0 replies
  Started over 16 years ago
  by BillAcito
• Discussion

  Sroute and vias in Encounter Locked

  14296 views
  0 replies
  Started over 16 years ago
  by konx
• Discussion

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  15748 views
  4 replies
  Latest over 16 years ago
  by Philey
• Discussion

  Follow rails for empty rows. Locked

  14149 views
  3 replies
  Latest over 16 years ago
  by Kari
• Discussion

  How to 'dbGet' the numeric "WireId" for a layer Locked

  948 views
  1 reply
  Latest over 16 years ago
  by BobD
• Discussion

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  17214 views
  2 replies
  Latest over 16 years ago
  by mcatramb91
• Discussion

  Global change of line width Locked

  13484 views
  3 replies
  Latest over 16 years ago
  by jch teyssier
• Discussion

  Verilog Monitor to Check 'X' state of a Clock from the DUT. Locked

  8062 views
  2 replies
  Latest over 16 years ago
  by Mickey
• Discussion

  Spectre Simulation using IBM_PDK and ARM Std Cell Libraries Locked

  15147 views
  2 replies
  Latest over 16 years ago
  by Andrew Beckett
• Discussion

  IDF: ECAD/MCAD File Transfer Locked

  3168 views
  4 replies
  Latest over 16 years ago
  by Randy R
• Discussion

  what is the SKILL code to get the padstack info such as drill diameter and pad size

  14385 views
  1 reply
  Latest over 16 years ago
  by eDave
• Discussion

  ELC(Encounter Library Characterization)(Ex-Signalstorm) isues Locked

  1723 views
  2 replies
  Latest over 16 years ago
  by admin