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  • Discussion

    Too much manual fixing. Locked

    14730 views
    5 replies
    Latest over 16 years ago
    by potat0e
  • Discussion

    dataType in pcDefinePCell Locked

    17731 views
    5 replies
    Latest over 16 years ago
    by dmay
  • Discussion

    Allegro to Altium Conversion help Locked

    16848 views
    3 replies
    Latest over 16 years ago
    by deac
  • Discussion

    Setting the position of a db or rod object Locked

    15582 views
    2 replies
    Latest over 16 years ago
    by Austin CAD Guy
  • Discussion

    PCAD to Allegro Locked

    14993 views
    4 replies
    Latest over 16 years ago
    by deac
  • Discussion

    Changes to padstacks/updating to design Locked

    3554 views
    7 replies
    Latest over 16 years ago
    by Carvey
  • Discussion

    Antenna Vias? Locked

    19048 views
    2 replies
    Latest over 16 years ago
    by steve
  • Discussion

    reset tree generation in Encounter Locked

    14610 views
    2 replies
    Latest over 16 years ago
    by archive
  • Discussion

    hdl_path() for sys: error in specman v5.1 Locked

    14207 views
    1 reply
    Latest over 16 years ago
    by StephenH
  • Discussion

    How to create shielded path? Locked

    17954 views
    6 replies
    Latest over 16 years ago
    by infy
  • Discussion

    Connecting System Verilog to VHDL data type Locked

    14347 views
    0 replies
    Started over 16 years ago
    by cpehaot
  • Discussion

    DBIDs and 16.2

    14212 views
    3 replies
    Latest over 16 years ago
    by dgstan
  • Discussion

    CS_CLUSTERETCH ??? Locked

    12538 views
    0 replies
    Started over 16 years ago
    by Nakji
  • Discussion

    Artwork control form Locked

    14531 views
    4 replies
    Latest over 16 years ago
    by Carvey
  • Discussion

    Map functions

    14590 views
    4 replies
    Latest over 16 years ago
    by aCraig
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