• Discussion

  Number of Non Equivalence Points after comparison in LEC Conformal Locked

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  1 reply
  Latest over 17 years ago
  by Azhar
• Discussion

  timing_type : non_seq_hold_falling; Locked

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  0 replies
  Started over 17 years ago
  by guyra
• Discussion

  Multi Value List in 'e' Locked

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  2 replies
  Latest over 17 years ago
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• Discussion

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  4 replies
  Latest over 17 years ago
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• Discussion

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  6 replies
  Latest over 17 years ago
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• Discussion

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  3 replies
  Latest over 17 years ago
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• Discussion

  DEHDL Global Update of changed PTF key properties Locked

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  Latest over 17 years ago
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• Discussion

  Of interest: "Chips-in-a-SiP” are a circuit simulation headache"

  677 views
  0 replies
  Started over 17 years ago
  by archive
• Discussion

  A printf wrapper Locked

  14340 views
  1 reply
  Latest over 17 years ago
  by dmay
• Discussion

  Orcad layout plus Locked

  14563 views
  3 replies
  Latest over 17 years ago
  by oldmouldy
• Discussion

  How to set pins' connection in SOC encounter? Locked

  6095 views
  2 replies
  Latest over 17 years ago
  by Renee
• Discussion

  Disable clock gating check for a module. Locked

  16546 views
  0 replies
  Started over 17 years ago
  by Tongju
• Discussion

  Adding drill holes Locked

  17470 views
  5 replies
  Latest over 17 years ago
  by Mattski
• Discussion

  Merging ICFB and SOC Encounter Locked

  13694 views
  1 reply
  Latest over 17 years ago
  by BobD
• Discussion

  How to stream in Verilog to Virtuoso using "Retain reference library (No Merge)" Locked

  2973 views
  3 replies
  Latest over 17 years ago
  by BobD