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Answered

Need help with TCL code to modify offpage 0

13863 views

7 replies

Latest over 1 year ago
by CadAP
Not Answered

Alegro X System Capture Smart PDF Does Not Print Attribute 0

2847 views

2 replies

Latest over 1 year ago
by NM202507313145
Discussion

DRC Violations due to Macro Placement and Power Straps in Innovus Stylus Flow Locked

5328 views

0 replies

Started over 1 year ago
by XL202501136611
Answered

Allegro issue 17.4 +1

4091 views

5 replies

Latest over 1 year ago
by John T
Discussion

How to expand (uncollapse) waveforms (before saving them in Viva) Locked

2701 views

2 replies

Latest over 1 year ago
by leok
Discussion

How to load viaGetViaOptions Function inside PCELL Locked

3074 views

4 replies

Latest over 1 year ago
by Andrew Beckett
Answered

Allegro 16.6 Setup files +1

2584 views

1 reply

Latest over 1 year ago
by vidhyaparameswari
Discussion

White phase noise in VCO decays with frequency – not flat as expected Locked

4178 views

1 reply

Latest over 1 year ago
by Andrew Beckett
Discussion

Same net shape to via spacing when a via edge touches the shape: how to set the shape to void the via edge?

16165 views

10 replies

Latest over 1 year ago
by avant
Discussion

Any analogue or mixed signal Cadence FinFet layouts to share? Locked

2167 views

0 replies

Started over 1 year ago
by hesaliveJim
Answered

Pointwise Grid Solve Feature 0

4198 views

3 replies

Latest over 1 year ago
by Claudio M Pita
Discussion

verilog Syntax errors not highlighted in text editor Locked

5231 views

6 replies

Latest over 1 year ago
by JavierC
Discussion

How to manage block-level and top-level SDC constraints? Locked

5418 views

0 replies

Started over 1 year ago
by MichR
Suggested Answer

Junction Dots - Why are they unfilled in PDF? How to fix? 0

1607 views

1 reply

Latest over 1 year ago
by rg13
Answered

How to properly move a part between OLBs with TCL? 0

10030 views

11 replies

Latest over 1 year ago
by andakConsultingLtd