• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    ncvlog netlist generation Locked

    14242 views
    1 reply
    Latest over 7 years ago
    by Andrew Beckett
  • Discussion

    Transient Analysis-plotting frequency vs input voltage Locked

    24486 views
    3 replies
    Latest over 7 years ago
    by Andrew Beckett
  • Discussion

    Custom Independent Current Sources Locked

    18212 views
    1 reply
    Latest over 7 years ago
    by Andrew Beckett
  • Discussion

    SpiceIn- MOS size matching problem Locked

    6148 views
    1 reply
    Latest over 7 years ago
    by Quek
  • Discussion

    3D Canvas unexpected changes and how to? Locked

    13659 views
    1 reply
    Latest over 7 years ago
    by DavidJHutchins
  • Discussion

    Going back to old schematic symbol editor interface (pre 17.2 S042) Locked

    16021 views
    6 replies
    Latest over 7 years ago
    by dac22
  • Discussion

    Set Library source to ddHiCreateCellComboField. Locked

    16867 views
    2 replies
    Latest over 7 years ago
    by iguerra
  • Discussion

    Opening MAX2870 .PCB and .SCH files Locked

    14673 views
    0 replies
    Started over 7 years ago
    by coldmatt
  • Discussion

    SKILL code to change all the existing Metal layers to its corresponding fillBlock layer Locked

    20434 views
    9 replies
    Latest over 7 years ago
    by Andrew Beckett
  • Discussion

    Bus-expansion-like trick for an array of design variables Locked

    17704 views
    2 replies
    Latest over 7 years ago
    by fastandig
  • Discussion

    Creating Netlist--Error(ORCAP-32007):Netrev failed. Please refer to Session log or netrev.lst for details. Locked

    12174 views
    7 replies
    Latest over 7 years ago
    by steve
  • Discussion

    What am i doing wrong? Locked

    14864 views
    4 replies
    Latest over 7 years ago
    by ssram
  • Discussion

    Sigrity OptimizePI "Error occurred while doing what-if analysis based on shorted decaps." Locked

    845 views
    0 replies
    Started over 7 years ago
    by In2p3SubRenard
  • Discussion

    License fails abruptly in while working on ORCAD. Locked

    14666 views
    0 replies
    Started over 7 years ago
    by jishu
  • Discussion

    for choosing the frequency range of any digital circuit Locked

    13926 views
    0 replies
    Started over 7 years ago
    by jayakandpal
<>

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information