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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

Demystifying Verification of PCIe 6.0 Equalization

The PCI-SIG Developers Conference 2024 is poised to be the premier event for professionals…

• 6 min read
Verification IP , equalization , PCIe , PCIe 6.0 , Training Sequences

Verification Using Near End Loopback

Near End Loopback (NELB) is a feature introduced by Intel's PHY Interface spec revision…

• 2 min read
Verification IP , NELB , PHY DUT

Enhancing Verification Processes with Session Composer: A Path Toward Efficiency

The complexity and volume of regression tests can be overwhelming in the domain of…

• 2 min read

Debugging SystemVerilog Constraint Randomization: A Comprehensive Guide

Introduction SystemVerilog constraint randomization is a powerful methodology for…

• 4 min read
SystemVerilog , Constraint Random , uvm , debug , verisium , Verisium Debug

PCIe 6.0 Address Translation Services: Verification Challenges and Strategies

Address Translation Services (ATS) is a mechanism in PCIe that allows devices to…

• 4 min read

Industry's First Adopted VIP for PCIe 7.0

Overview of PCIe 7.0 Technology PCIe technology has evolved over three decades…

• 2 min read
pcie gen7 , Cadence VIP portfolio , VIP , PCIe 7.0 , PCIe

Unraveling the PCIe ECN Unordered IO (UIO) Feature

Introduction Unordered IO (UIO) ECN is included in the PCIe 6.1 specification and…

• 3 min read
Verification IP , Functional Verification , PCIe 6.0 , PCI Express , verification

Unveiling NOP Insertion Hint: A Performance Optimizer in CXL 3.0

Compute Express Link (CXL) is a high-speed interconnect standard that facilitates…

• 3 min read
256BLOptMode , CXL3.0 , Latency Optimization , NOP Insertion Hint , latency

Tools of the Future: How Cadence Is Using AI to Change Verification

Generative AI is sweeping through every industry, re-writing the way things are done…

• 3 min read
autotriage , Functional Verification , verisium , pindown , codeminer , AI , waveminer

Navigating the Future of EDA: The Transformative Impact of AI and ML

The landscape of electronic design automation (EDA) is undergoing a monumental transformation…

• 3 min read
artificial intelligence , ml , EDA , AI/ML , podcast , AI

Unraveling the Newly Introduced Segmentation in PCIe 6.0

Overview The PCIe protocol evolved to its sixth generation in 2021, doubling its…

• 4 min read
verification strategy , Functional Verification , System Design and Verification , VIP , SoC , PCIe

Real Number Modeling Streamlines Mixed-Signal Verification

Semiconductor design is swiftly evolving, with mixed-signal design playing a pivotal…

• 4 min read
Functional Verification , Mixed Signal Verification , Xcelium Logic Simulator , Mixed-Signal , RNM , mixed signal , verification , EEnet

USB4 Version 2.0 – Gen4 Link Recovery

USB4 Version 2.0 specification was released by the USB Promoter Group two years back…

• 2 min read
USB4 VIP , USB4v2 , usb4 , USB4 Version 2

Advancing Digital Verification with Dynamic Duo III's Accelerated Computing

In an era where the complexity of chip design is accelerating at an unprecedented…

• 5 min read

Speedy Gate-Level Simulation with Xcelium Multi-Core - Northrop-Grumman's Story

We all know the benefits of gate-level simulation, but we also all know the pain…

• 3 min read
RTL , northrup grumman , Multi-Core , gate-level , xcelium multi-core , xcelium , testbench

Streamline PCIe 6.0 Switch Design with Effective Verification Strategies

The demand for PCIe 6.0 switches has surged due to the exponential growth in global…

• 4 min read
non flit mode , Functional Verification , switch , VIP , switch performance , PCIe 6.0 , flit mode

Training Insights: Introducing the C++ Course for All Your C++ Learning Needs!

This course, "C++ Fundamentals for Design and Verification v24.03" provides an introduction…

• 2 min read
C++ , verification

USB4 Version 2.0 – Low Power with Gen4 Link

USB4 Version 2.0 specification was released by the USB Promoter Group two years back…

• 3 min read
USB4 VIP , USB4v2 , usb4

Cooking Up Better Performance for Arm-Based SoCs

With increasing complexity, ascertaining performance in Arm-based SoCs design has…

• 3 min read
featured , chiplets , Arm-based SoC , cadencelive , ARM , Arm Performance cookbook

Exploring the Security Framework of RISC-V Architecture in Modern SoCs

Introduction to System on Chip (SoC) Security In the rapidly evolving world of…

• 2 min read
security , PMP , risc-v , cadence , SoC , mediatek

Integrating Coherent RISC-V SoCs: Advanced Solutions with Perspec

In the rapidly evolving Systems on Chips (SoCs) landscape, the need for more efficient…

• 2 min read
SoC verification , risc-v , Perspec , RISC , coherency

RISC-V: Democratizing Innovation in CPU Design

RISC-V has emerged as a groundbreaking force in the semiconductor industry, fundamentally…

• 3 min read

Cadence Memory Models - The Gold Standard

In today’s world, we’ve been seeing an unprecedented rise in the use of “data” with…

• 4 min read
Verification IP , Functional Verification , Cadence VIP portfolio , VIP , memory models

Testing and Training HBM (High Bandwidth Memory) DRAM Using IEEE 1500

HBM is a JEDEC (Joint Electron Device Engineering Council) standard-defined DRAM…

• 3 min read
Verification IP , uvm , Functional Verification , Cadence VIP portfolio , System Design and Verification , VIP , Memory Model Portfolio , memory models , verification

Serial NAND Flash: New Octal SPI Dual Data Rate Capabilities

Serial NAND Flash NAND Flash has been in a constant battle to prove its competitive…

• 5 min read
Verification IP , Functional Verification , NAND flash controller , serial flash , VIP , octal spi , flash memory , Memory Model , MMAV

Riding the AI Wave Using HBM (High Bandwidth Memory)

The ever-increasing innovations in artificial intelligence (AI) are revolutionizing…

• 3 min read
Verification IP , uvm , Functional Verification , Cadence VIP portfolio , System Design and Verification , VIP , Memory Model Portfolio , memory models , verification

LPDDR5X Opening New Markets for Low-Power DRAMs

Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor…

• 4 min read
Verification IP , Low Power DRAMs , Memory , LPDDR Market , LPDDR , VIP , JEDEC , lpddr5 , lpddr5x , verification

Cadence Introduces the Industry’s First GDDR7 Verification Solution

GDDR7 Introduction In February 2024, JEDEC announced the successor to GDDR6 with…

• 3 min read
Verification IP , Functional Verification , Cadence VIP portfolio , memory models , GDDR7 , System Design and Verification
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