• DAC DFM Coalition - Do You Work On Sunday Afternoons?

    It was a sunny, Sunday afternoon in Anaheim (across from Disneyland). That combination of weather and entertainment didn't sway a group of 35 engineers from participating in the DFMC (Design for Manufacturability Coalition) Workshop at DAC 2010.

    • 14 Jul 2010
  • Tidbits From TSMC Q209 Earnings Call - 40nm Yield

    Earning calls sure are interesting! Below is an excerpt from the TSMC Q209 call (transcript from seekingalpha). The discussion revolves around the 40nm yield issues and TSMC's ramp to improving the yield.

    Dr. Liu really hits on a key element of DFM...

    • 7 Aug 2009
  • Moore no More

    "The number of watchmen required to watch the watchmen watching the watchmen tends to double every 18 months".  This gem is Alan Moore's law, posted years ago by some wag in response to an Intel article on geek.com.  This has, of course, surfaced because of the recent release of the Watchmen movie.  OK so I admit that I haven't read the book or even seen the movie - and based on my recent experiences of superhero…

    • 10 Apr 2009
  • Assura Foundry Support

    I've been blogging a lot about Assura recently, so I thought I would continue by talking about rule decks. 

    Inside Cadence, we maintain a database that shows which foundries support which process for which products.  This means that we can quickly give you an answer if you are considering using a new process or foundry, and you want to know whether Assura is supported.  Your friendly local Cadence physical verification…

    • 23 Mar 2009
  • Assura On Steroids

    In a recent post, I hinted at a significant performance improvement in Assura

    Our R&D team focused on performance improvements in the 3.2 release, which was shipped last August.  Based on our suite of performance benchmarks, we achieved an overall 10x performance boost.  This comes from two fundamental improvements: an overall 3.5x boost in single processor performance, and an overall 2.8x performance boost from using…

    • 17 Mar 2009
  • ERC in Assura II

    In my last post I talked about the layout, schematic and netlist ERC capabilities of Assura. 

    "But", I hear you ask, "is it programmable?"

    One of the characteristics that makes Assura such a natural fit within the Virtuoso custom design platform is that it shares the platform's programming language, SKILL.  So yes, it's programmable - in the very same language that your Pcells are written in…

    • 10 Mar 2009
  • The Buzz Around New Business Models

    The buzz about showing and paying for value in EDA has been building over the past few years. People have complained about the high cost of tools and EDA vendors have complained about not getting enough value from the technology that can then be re-invested in the next generation tools. The same complaints can be heard from the foundries regarding their wafer pricing

    Companies have tried royalty-based models before in…

    • 6 Mar 2009
  • ERC in Assura

    A few customers have recently asked whether we can provide schematic-based ERC checks.  This is no doubt spurred by a recent product announcement by one of our competitors.  No - I'm not going to say who, and I'm not going to provide a link to their product page. 

    We have had layout-based ERC checks as part of our Assura physical verification product since release 3.2 became available last August.  A quick check with…

    • 5 Mar 2009
  • Big Bang

    When something big and expensive fails, we usually hear about it in the headlines.  Recent examples include the launch failure of the Orbiting Carbon Observatory and the setback at CERN, apparently caused by a dry solder joint, that resulted in a 12-month delay in their search for the Higgs particle

    When something small and cheap fails, it rarely makes the headlines.  Unless, of course, it causes something big and expensive…

    • 2 Mar 2009
  • All For One

    Finally, sanity.  Concerned about the level of electronic waste created by discarded phone chargers, the European Commission has told mobile phone manufacturers that they must adopt a standard.  This will hopefully have the additional advantage of reducing blood pressures if we no longer need to rummage in our desk drawers frantically searching for the right charger. 

    I wonder whether manufacturers would have voluntarily…

    • 23 Feb 2009
  • Coffee, Anyone?

    How little the world changes.  Back in the days of 68000-based workstations, we would open up a design and retreat to the break room for a coffee while it loaded.  Now, in the gigabyte / multicore era, we open up a design and retreat to the break room for a coffee.  Moore's law clichés aside, semiconductor design is sometimes reminiscent of lifting oneself by the bootlaces.  We produce faster and more powerful…
    • 13 Jan 2009
  • Getting Good Silicon With More Accurate Timing

    In these difficult economic times, achieving silicon success (functional and meeting specs) within an iteration becomes an even higher priority than before; there might not be a second chance to win that socket or hit that sales window.

    To that end, there appears to be a heightened interest in variation-aware methodologies to more accurately predict the electrical characteristics due to manufacturing/process variation…

    • 9 Jan 2009
  • Diagnosis of Compressed Test Patterns: Several Things to Consider

    Today, it is essential to put into place a strong methodology to identify sources of yield loss during manufacturing.  One widely accepted method involves diagnosing a representative sample of device failures during manufacturing test.  The failing results are aggregated, analyzed and a Pareto is created showing the highest frequency of failures from one or more of: cell, instance, net, test pattern, metal layer and layout…

    • 21 Oct 2008
  • Video interviews from the floor of CDNLive!

    With hundreds of attendees buzzing about, our video crew has been busy with their “man-on-the-street” style interviews from the floor of “CDNLive! Silicon Valley 2008” here at the San Jose Convention Center.

    The “CDN” in the name stands for “Cadence Designer Network.”  This week’s conference is part of a worldwide series of meetings where Cadence power-users can network with…

    • 10 Sep 2008
  • What works best?

    Today's conventional wisdom tells us EDA folks the majority of yield loss at semiconductor companies is due to systematic issues, that's what my customers say to me. When I speak with new prospective users of my yield ramp solution, I normally see concurring facial expressions when I mention this as the most pressing problem facing product engineers.

    Given this apparent reality, the majority of manufacturing failu…

    • 14 Aug 2008
  • Please allow me to ...

    In the words of the Rolling Stones…. Please Allow Me to Introduce Myself ,,,,, I took a different slat than Chris on my intro but I am a Product Marketing Director for Cadence's Diagnostics and silicon analysis products.  I also have over 20 years of EDA experience and began my career as a test engineer working on hardware accelerators. I have held various positions in field applications and product marketing in…
    • 6 Aug 2008
  • Anyone involved in managing OPC or DFM may want to read this

    There is a good article in the August edition of Microlithography World that anyone involved in managing OPC or DFM may want to read. I may be a bit biased (I was one of the authors) but it is good......

    Here's a link to the article.

    Fujitsu, Applied Materials and Cadence collaborated for this article to discuss the process we used to help Fujitsu create CD-SEM recipes.   It was a great experience and our collaboration helps…

    • 6 Aug 2008
  • Do foundries care about yield?

    I was talking recently with a fabless semiconductor company whose designers were confused about their foundry's strategy for design-for-yield.  They asked me whether they should follow the foundry's guidelines on yield, or formulate their own yield strategy to complement what the foundry had recommended. 

    I asserted that yield is much too important to leave to the foundry.  In most cases, foundries are in the business…

    • 5 Aug 2008
  • DFM in Disguise

    DFM is an overloaded acronym/word. In some design flows, DFM can be found front-and-center and in others, it is just along-for-the-ride. It may be disguised as more rules in a process/rules design manual, or it can be quite explicit in a model-based analysis and optimization flow.

    But wait, let's get through some of the formalities... My name is Wilbur and I'm an engineering manager in the front-end DFM space. My focus…

    • 12 Jul 2008
  • Allow myself...

    In the words of Austin Powers, "Allow myself to..." - well you get the idea. 

    I'm Chris, and I am a Senior Product Marketing Manager for a number of Cadence physical verification, yield analysis and mask design products.  I have about 20 years in EDA under my belt.  My professional interests include product marketing for early and late lifecycle products.  Outside interests include cosmology and health/fitness…

    • 11 Jul 2008