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  • Discussion

    spectre save statements Locked

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    4 replies
    Latest over 16 years ago
    by Andrew Beckett
  • Discussion

    calculate bandwidth from Cadence Virtuoso 5.1.41 Locked

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    1 reply
    Latest over 16 years ago
    by Andrew Beckett
  • Discussion

    Implementation of Verilog-AMS in AMS Simulator Locked

    13013 views
    0 replies
    Started over 16 years ago
    by Emmanuele
  • Discussion

    Questions on testbench / toplevel schematic automation Locked

    13739 views
    0 replies
    Started over 16 years ago
    by taow
  • Discussion

    Specman syntax errors Locked

    14743 views
    3 replies
    Latest over 16 years ago
    by StephenH
  • Discussion

    soldermask-to-line constraint Locked

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    5 replies
    Latest over 16 years ago
    by ahmetozsoy
  • Discussion

    Proper view of a package Locked

    13128 views
    2 replies
    Latest over 16 years ago
    by girish
  • Discussion

    help on ETS & RTL compiler Locked

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    1 reply
    Latest over 16 years ago
    by grasshopper
  • Discussion

    Declaring analog power Locked

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    1 reply
    Latest over 16 years ago
    by BobD
  • Discussion

    Simvision: Colored an hexadecimal signal according to its value Locked

    16430 views
    2 replies
    Latest over 16 years ago
    by Yaira
  • Discussion

    Greping all loaded e modules for a regular expression Locked

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    2 replies
    Latest over 16 years ago
    by avidane
  • Discussion

    finding vias

    15493 views
    4 replies
    Latest over 16 years ago
    by ahmetozsoy
  • Discussion

    update for thermal relief with a flash for gnd pin-PCB L 16.2

    14242 views
    4 replies
    Latest over 16 years ago
    by Adeel
  • Discussion

    prBoundary translation Locked

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    2 replies
    Latest over 16 years ago
    by sooky
  • Discussion

    Verify Net schedule (daisy chain) using Constraint Manager Locked

    13623 views
    1 reply
    Latest over 16 years ago
    by David G
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