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Forum - Thread List
  • Discussion

    inductor LVS and netlisting Locked

    12309 views
    5 replies
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    Keysight ADS schematic into Virtuoso Locked

    11019 views
    2 replies
    Latest over 3 years ago
    by sidm
  • Answered

    Page numbering on Hierarchical blocks 0

    19185 views
    6 replies
    Latest over 3 years ago
    by briwei
  • Discussion

    Can Verilog-A macro names be swept in Corners Setup of ADE Assembler for Spectre simulations? Locked

    10150 views
    2 replies
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    Missing Corner Setups ADE Explorer Locked

    10712 views
    2 replies
    Latest over 3 years ago
    by Kevin Buck
  • Discussion

    SysCap - Tip of the Week: Highlighting net on a page

    1096 views
    0 replies
    Started over 3 years ago
    by DesignTech
  • Discussion

    Genus synthesis report Locked

    15501 views
    2 replies
    Latest over 3 years ago
    by Kelly Yu
  • Not Answered

    Can't zoom in and out when using certain hotkeys. 0

    1881 views
    1 reply
    Latest over 3 years ago
    by mstaub
  • Discussion

    Could Virtuoso VXL or SKILL code report missing via on the same net Locked

    10329 views
    2 replies
    Latest over 3 years ago
    by mctang21
  • Answered

    Failed to import schematic from EAGLE. sch to ORCAD 0

    11180 views
    5 replies
    Latest over 3 years ago
    by ZhengweiX
  • Discussion

    File system path do Documents Locked

    10108 views
    2 replies
    Latest over 3 years ago
    by dragank
  • Discussion

    Organize your part data better with CIS: CIS-2

    7844 views
    0 replies
    Started over 3 years ago
    by DesignTech
  • Discussion

    Monte Carlo Simulation Results Canceled Locked

    9482 views
    1 reply
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    Allegro - Tip of the week: Sliding vias/clines freely into dynamic shapes

    1476 views
    0 replies
    Started over 3 years ago
    by PCBTech
  • Discussion

    Layers visibility issue in hierarchical layout design Locked

    9882 views
    2 replies
    Latest over 3 years ago
    by Senan
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