• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    How to determine if an instance is a frozen p-cell? Locked

    10947 views
    4 replies
    Latest over 3 years ago
    by Byron Caloz
  • Discussion

    converting an analog signal into digital and saving the formula on the ADE outputs Locked

    13854 views
    2 replies
    Latest over 3 years ago
    by TommasoF
  • Discussion

    automatic routing using specific metal layer Locked

    10819 views
    1 reply
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    How to add dyn_floatdcpath into ADE Locked

    9775 views
    1 reply
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    How to Model a Filter in VerilogA other than laplace function? Locked

    13323 views
    3 replies
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    How to create vhdl view and symbol from an existing vhdl cdoe? Locked

    12023 views
    2 replies
    Latest over 3 years ago
    by bikram1994
  • Discussion

    Apply 'and/'or to a list of lists Locked

    1638 views
    2 replies
    Latest over 3 years ago
    by AurelBuche
  • Discussion

    is there something like "Net Highlighting" in the layout? Locked

    2927 views
    2 replies
    Latest over 3 years ago
    by delgsy
  • Discussion

    How to set optimization goals to output equations using MWO in AWR

    10650 views
    0 replies
    Started over 3 years ago
    by SimTech
  • Not Answered

    CIP Server installation issue: password is too short 0

    13441 views
    6 replies
    Latest over 3 years ago
    by Luc S
  • Discussion

    Importing Digital Standard Cells from PDK data Locked

    10890 views
    0 replies
    Started over 3 years ago
    by Matthias Ochs
  • Discussion

    Running "small environment" on specview Locked

    3951 views
    4 replies
    Latest over 3 years ago
    by Nir Z
  • Discussion

    Preventing Instantiation of Cells from Restricted Library Locked

    13661 views
    9 replies
    Latest over 3 years ago
    by Kevin Buck
  • Discussion

    Find all libraries used in design hierarchy Locked

    11303 views
    2 replies
    Latest over 3 years ago
    by MorrisDH
  • Discussion

    Issue with Import ADE-XL State to Cadence Explorer. Locked

    9243 views
    1 reply
    Latest over 3 years ago
    by GirishW
<>

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information