Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I am not sure about what
PVT corner I should use for worst case power analysis. I have
identified two things in LIB files which are affected by PVT corner
selection and affects power analysis:
internal and leakage power;
Temperature selection is
ok! When we increase temperature we increase power consumption since
both k_factors and transition time are directly proportional to
temperature (power consumption of a cell depends on input transition
The problem is for process
and voltage selection:
decreases when we increase operating voltage (inversely
proportional), in contrast of k_factors. So, I should select low or
high voltage for worst case power analysis?
increases when we increase process value (directly proportional), in
contrast of k_factors. So, I should select low or high process for
worst case power analysis?
Besides that, most of LIB
files describes PVT corners only for STA and these corners are
different for power analysis. So, it is needed define new corners in
LIB files to perform worst case power analysis?
Anyone can help me?
Thanks in advance...
I can certainly commiserate with you, my libraries are also setup for timing PVT points.Can I ask how accurate do you need your power estimate to be? In my experience, the inaccuracies in things like activity estimation, library data etc will tend to make the values measured with real silicon somewhat different to the pre-tapeout estimations (and even more different to RTL level estimation of power). What I do know however is that the relative saving of using a technique will be accurate between the estimation and the silicon.I know some tools allow values for P V & T to be set independent of the actual library fixed points, but I'm not sure if this is available in all Cadence tools.Chris
I am using simulation based analysis (with VCD files) because I think that is the most accurate analysis which is possible to perform using Encounter. Is it right?I know that any gate-level analysis will result in a power estimation somewhat different to measured values, but I think it is the best power estimation I can do at this design step. I intend to use this type of analysis to optimize power consumption once, as you have said, relative power savings will be valid in real silicon measurements. I tried overcome the problem of existing only PVT corners for timing in my LIB files by creating a new “dummy” LIB file just to specify power PVT corners. And it seems be ok!But my main problem is identify the right corner values for process and voltage to perform a safe power analysis. As I have stated in previous message, choosing best/worst values for voltage or process increases power through transition time but at the same time decreases power through k_factors, and vice-versa...So, it is better chose best or worst values for process and voltage to guarantee a safe power analysis?
Simulation based analysis is by far the most accurate, but care is needed to ensure that you really have accurate use-cases for your block or chip in simulation. For example, I'm heavily involved with SoC integration, and although my team has testcases for IP blocks in the chip, these are typically only stressing the interface so we can ensure the integration is correct. It is less common for us to run simulations stressing each IP to ensure that it is performing it's own internal functions correctly (really depends on the source and complexity of the IP: I might test a Uart to the fullest extent, but a DSP that has been used on other products may only have a brief interface test). Thus if I were to use these sims as a basis for power-analysis, I may or may not get an accurate picture of the power consumption. So I tend to have to base my analysis on statistical analysis. As for which point to use for the actual analysis, yes I understand your problem. I don't think there is a right or wrong answer. I personally run my analysis at the worst-case timing PVT point, and don't worry if this is the worst power point. If I run all of my analysis at the same operating conditions, then the effect of design changes is surely valid. Also, since both my synthesis and layout tools are using this PVT to do optimisation for timing, then it makes sense to base all of my analysis here.Of course, if you are trying to see what effect making the design [i]high-Vt and std Vdd[/i] compared to [i]low-Vt with reduced Vdd[/i], then you could well see "savings" which are caused by the different operating points.You say that you've tried making dummy PVT points that match (suspected) power corners rather than timing corners. Can you run your analysis and tell us what difference P, V and T have on estimated dynamic and static power? My own gut feel is that the power increase caused by higher transition times will be less than that caused by higher voltages since power is just proportional to frequency, but is proportional to the square of the voltage.Chris
I agree with you that simulation based analysis depends a lot on used testcases. I think is a good idea develop specific testcases for power analysis.Concerning PVT for power analysis, I think if you have a power constraint, for example, you need to know if your design can reach this constraint and so worst case power consumption is important. In addition to that, worst case power analysis will give you the worst case IR drop and as far as I know it is needed to run STA considering this worst case IR drop (I have another doubt concerning STA using results of IR drop analysis, but I will post it in another topic).Your felling seems to be correct, the worst case power analysis if for worst voltage and temperature and best process (I will post the results for all corners analysis as soon as I organize them).Regards,Cristiano L. Santos
I used a small block of an rfid tag of 5Kgates operating at very low frequency (640KHz) and I tested these PVT combinations:Case 1: WORST extraction, HIGH temperature, HIGH voltage, BEST process => 1.2637e-01 mWCase 2: WORST extraction, HIGH temperature, LOW voltage, BEST process => 7.8231e-02 mW Case 3: WORST extraction, HIGH temperature, HIGH voltage, WORST process => 1.0015e-01 mwCase 4: WORST extraction, HIGH temperature, LOW voltage, WORST process => 6.4237e-02 mwCase 5: BEST extraction, LOW temperature, LOW voltage, WORST process => 5.3186e-02 mCase 6: BEST extraction, LOW temperature, HIGH voltage, WORST process => 8.3718e-02 mwCase 7: BEST extraction, LOW temperature, LOW voltage, BEST process => 6.9326e-02 mwCase 8: BEST extraction, LOW temperature, HIGH voltage, BEST process => 1.1280e-01 mwAs you have said, both voltage and process have more influence on cell delay by k_factors than by the increase of transition times. So, I will use “Case 1” as PVT point to estimate the worst IR drop.Thanks,Cristiano.
If you really want to find the worst power. You can probably measure it on 2 cycles with a VCD from an ATPG at speed test. This will try to toggle as many FFs as possible in your designs, ignoring protocols and everything else. Then take case 1 above and you probably have yourself in your worst case scenario. Actually you can probably make it even worst by using an overdrive voltage of the type that might be used to age the part during characterization. Then of course you have the question of what do I do with that? my guess is nothing as if you design to support that you will most likely explode your design constraints. (which is why a lot of people are working on different approach to reduce test power requirement without killing test time) Of course I agree with Chrys's statement which I believe give an accurate view of what is being done today with the exception of analyzing thing such as leakage power in stand by mode which may not be as important for your design but is crucial for some application (battery life anyone?).In my personal opinion the critical items of today's design regarding power are: 1. Simulations providing realistic use case scenario. (note that 1 is not enough especially for SOC as various area of the design might be active at different time) 2. Accurate IR drop backannotation and usage in STA/Power analysis tools (requires accurate modeling) 3. Accurate glitch analysis. 4. Signal EM analysis 5. Good decap requirement prediction (in order to help with peak power requirement without killing leakage) 6. Education of the whole management/Customer chain i.e. There is not a single power number for a chip it all depends on use scenario.Now I would love to hear about what you guys are doing for each of the problems above and also if anybody as looked at SSTA like approach to power analysis i.e. the chip is not in case 1 or case 2 above but in a combination of the various parameters. Thanks,Eric.