Custom IC Design

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Discussion

Open Layout-L instead Layout-XL by default (even if phsyconfig exists)

Category: Custom IC Design

By HoWei

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updated over 4 years ago by mjchoe

5 replies • 20993 views
Discussion

Setting up a jitter simulation for Ring Oscillator

Category: Custom IC Design

By harish patruni

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updated over 4 years ago by FormerMember

3 replies • 18980 views
Discussion

Liberate AMS GUI: arc present in log file, but not generated in .lib file

Category: Custom IC Design

By stagro

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updated over 4 years ago by Guangjun Cao

8 replies • 14115 views
Discussion

How to execute an Ocean command from a string

Category: Custom IC Design

By BobS893

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updated over 4 years ago by Andrew Beckett

3 replies • 11925 views
Discussion

Problems with transistor operation point info in transient analysis

Category: Custom IC Design

By greywanderer

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updated over 4 years ago by greywanderer

2 replies • 11298 views
Discussion

Re-running a particular iteration of the montecarlo sims

Category: Custom IC Design

By greywanderer

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updated over 4 years ago by greywanderer

5 replies • 13412 views
Discussion

Measuring XStream performance in Virtuoso

Category: Custom IC Design

By knowledgeseeker

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started over 4 years ago

0 replies • 10186 views
Discussion

Parameterizable Voltage Controlled Oscillator Model

Category: Custom IC Design

By janisw

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updated over 4 years ago by FormerMember

5 replies • 15315 views
Discussion

Generating Liberty (.lib) File From Verilog-A Table Model

Category: Custom IC Design

By NKFET

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updated over 4 years ago by Guangjun Cao

3 replies • 14467 views
Discussion

How to add stop layers to annotation browser?

Category: Custom IC Design

By 94d33m

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started over 4 years ago

0 replies • 10080 views
Discussion

How to get phase noise from noise summary at paticular frequency?

Category: Custom IC Design

By Clara Dong

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updated over 4 years ago by FormerMember

2 replies • 11921 views
Discussion

Plotting a function on Cadence calculator that requires the temperature read from x-axsis

Category: Custom IC Design

By Senan

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updated over 4 years ago by FormerMember

3 replies • 13899 views
Discussion

How to make auto via feature in cadence avoid slot layers since it causes DRC violations?

Category: Custom IC Design

By 94d33m

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updated over 4 years ago by Alex Soyer

1 replies • 11119 views
Discussion

How to formulate the "best fit line" in Vertuoso calculator

Category: Custom IC Design

By Senan

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updated over 4 years ago by Senan

2 replies • 2648 views
Discussion

cross function deficiency

Category: Custom IC Design

By CADcasualty

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updated over 4 years ago by CADcasualty

2 replies • 11847 views

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