Custom IC Design

Latest Posts

Discussion

Large signal SNR with transient noise analysis

Category: Custom IC Design

By JoHi

$usertype
•
updated over 10 years ago by JoHi

3 replies • 16122 views
Discussion

Run RCX Problems

Category: Custom IC Design

By rafaelon

$usertype
•
updated over 10 years ago by Andrew Beckett

1 replies • 14506 views
Discussion

Verilog-A 2**integer yields wrong value

Category: Custom IC Design

By AlbertoGS

$usertype
•
updated over 10 years ago by Andrew Beckett

1 replies • 4177 views
Discussion

ADE-XL: How to force individual result directories for each Monte Carlo point?

Category: Custom IC Design

By dontpanic

$usertype
•
updated over 10 years ago by Andrew Beckett

24 replies • 30270 views
Discussion

What is the difference between Id and Ids notation in result browser

Category: Custom IC Design

By syafiq

$usertype
•
updated over 10 years ago by Andrew Beckett

1 replies • 18935 views
Discussion

pss/qpss in the same run (alter? in ADE L?)

Category: Custom IC Design

By itos

$usertype
•
updated over 10 years ago by Andrew Beckett

4 replies • 2937 views
Discussion

Netlisting failed with multiple Verilog-A blocks

Category: Custom IC Design

By ywyc

$usertype
•
updated over 10 years ago by Andrew Beckett

1 replies • 17368 views
Discussion

ams license queuing

Category: Custom IC Design

By analogcad2

$usertype
•
updated over 10 years ago by Sandeep4386

5 replies • 16128 views
Discussion

Generating a current waveform in Cadence

Category: Custom IC Design

By BaaB

$usertype
•
updated over 10 years ago by BaaB

2 replies • 15136 views
Discussion

Transient-Noise Analysis, problem with multiple run mode

Category: Custom IC Design

By Amir0098

$usertype
•
updated over 10 years ago by Amir0098

2 replies • 15446 views
Discussion

Problem with HSPICE Shooting Newton (SN) AC analysis in Cadence ADE

Category: Custom IC Design

By jdp721

$usertype
•
updated over 10 years ago by Andrew Beckett

1 replies • 15657 views
Discussion

how could i handle a dual-path PFD+CP structure when using noise aware PLL flow?

Category: Custom IC Design

By danglanggao

$usertype
•
updated over 10 years ago by Andrew Beckett

5 replies • 3566 views
Discussion

Using Subversion for Revision Control with Cadence

Category: Custom IC Design

By archive

$usertype
•
updated over 10 years ago by acook

9 replies • 22422 views
Discussion

ocnxlOutputExpr result wave - how to save to either csv or picture?

Category: Custom IC Design

By ChrHert

$usertype
•
started over 10 years ago

0 replies • 833 views
Discussion

Run ADE XL without netlisting each time

Category: Custom IC Design

By Nicusor

$usertype
•
updated over 10 years ago by rishi74

5 replies • 17924 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.