Custom IC Design

Latest Posts

Discussion

Virtuoso layout hierarchical copy contains mysterious residue from other libraries

Category: Custom IC Design

By chenyanw

$usertype
•
updated over 4 years ago by chenyanw

7 replies • 13934 views
Discussion

skip=cut inst=[...] statements being ignored

Category: Custom IC Design

By wignesb

$usertype
•
updated over 4 years ago by Andrew Beckett

3 replies • 1916 views
Discussion

Virtuoso Error

Category: Custom IC Design

By omiya

$usertype
•
updated over 4 years ago by Andrew Beckett

6 replies • 13093 views
Discussion

Printing out unconventional process-specific model parameter in ADE

Category: Custom IC Design

By MReza123

$usertype
•
updated over 4 years ago by MReza123

6 replies • 12383 views
Discussion

ams XCELIUM simulation pauses

Category: Custom IC Design

By Michael H

$usertype
•
updated over 4 years ago by amifsud

7 replies • 14674 views
Discussion

circuit prospector not finding structure

Category: Custom IC Design

By KurtKimber1

$usertype
•
updated over 4 years ago by KurtKimber1

2 replies • 10648 views
Discussion

AC Sim Output Setup Issues

Category: Custom IC Design

By greywanderer

$usertype
•
updated over 4 years ago by greywanderer

2 replies • 10621 views
Discussion

accepting 1st subckt definition when there are duplicate subckts

Category: Custom IC Design

By wignesb

$usertype
•
updated over 4 years ago by wignesb

4 replies • 12138 views
Discussion

Two Environment Setup Issues

Category: Custom IC Design

By Kevin Buck

$usertype
•
updated over 4 years ago by Kevin Buck

10 replies • 14396 views
Discussion

Simulation of voltage doubler

Category: Custom IC Design

By akmo

$usertype
•
updated over 4 years ago by John kaka

2 replies • 15379 views
Discussion

Overriding specifications with VAR("...") expressions

Category: Custom IC Design

By rod1

$usertype
•
updated over 4 years ago by Andrew Beckett

1 replies • 1267 views
Discussion

Can liberate use an encrypted hspice model?

Category: Custom IC Design

By sherryshe

$usertype
•
updated over 4 years ago by sherryshe

9 replies • 13959 views
Discussion

[SOI device]How to deal with the backgate pin (VBGP & VBGN) settings of devices with 5 terminals while running liberate?

Category: Custom IC Design

By sherryshe

$usertype
•
started over 4 years ago

0 replies • 1371 views
Discussion

It's the same problem as the person above. Please tell me the solution

Category: Custom IC Design

By chanho

$usertype
•
updated over 4 years ago by Andrew Beckett

1 replies • 715 views
Discussion

Transient simulation - adding noise after steady state

Category: Custom IC Design

By jehh

$usertype
•
updated over 4 years ago by Andrew Beckett

5 replies • 4601 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.