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Custom IC Design

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  • Discussion

    ADE didn't generate the correct when using spf through config

    Category: Custom IC Design

    By CambridgeLv

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    updated over 1 year ago by CambridgeLv

    4 replies • 2816 views
  • Discussion

    The env variable to set schematic find zoom

    Category: Custom IC Design

    By sjwprcker

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    updated over 1 year ago by Andrew Beckett

    3 replies • 4723 views
  • Discussion

    Modifying Model Groups based on Environmental Variable

    Category: Custom IC Design

    By jdsherman

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    updated over 1 year ago by Andrew Beckett

    1 replies • 4259 views
  • Discussion

    how to stop virtuoso opening the schematic cellview when I open the layout view?

    Category: Custom IC Design

    By BS202407197848

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    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 4798 views
  • Discussion

    [liberate] FAILED TO GET MOS MODEL FOR 'XMP32_0'!

    Category: Custom IC Design

    By sherryshe

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    updated over 1 year ago by Guangjun Cao

    3 replies • 1235 views
  • Discussion

    top level parameter transfer to lower level verilog-A block

    Category: Custom IC Design

    By MikeA

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    started over 1 year ago

    0 replies • 4312 views
  • Discussion

    How to write an equation to measure pk-to-pk jitter from eye diagrams

    Category: Custom IC Design

    By paramx

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    updated over 1 year ago by paramx

    4 replies • 5946 views
  • Discussion

    Issue with Spectre reliability analysis (negative aging)

    Category: Custom IC Design

    By Amel

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    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 4473 views
  • Discussion

    virtuoso schematic replace function

    Category: Custom IC Design

    By liangqunshan

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    updated over 1 year ago by liangqunshan

    2 replies • 4934 views
  • Discussion

    BlackBox with Assura LVS

    Category: Custom IC Design

    By SteS93

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    updated over 1 year ago by SteS93

    1 replies • 5974 views
  • Discussion

    Switching from voltage source to high impedance port in VerilogA: Convergence problem

    Category: Custom IC Design

    By mohthi3

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    started over 1 year ago

    0 replies • 4042 views
  • Discussion

    How to decrease the capacitance of charging and discharging at the MSB of current steering DAC

    Category: Custom IC Design

    By Phd SA88

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    updated over 1 year ago by Andrew Beckett

    2 replies • 4404 views
  • Discussion

    Problem netlisting AV_Extracted from QRC extraction

    Category: Custom IC Design

    By Svilen64

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    updated over 1 year ago by Andrew Beckett

    1 replies • 4283 views
  • Discussion

    Boolean Operations in MarkNet file

    Category: Custom IC Design

    By Betoo

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    started over 1 year ago

    0 replies • 3843 views
  • Discussion

    Passing model file as parameter

    Category: Custom IC Design

    By Aro

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    •

    started over 1 year ago

    0 replies • 3867 views
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