Custom IC Design

Latest Posts

Discussion

Include CDF callback parameters in netlist

Category: Custom IC Design

By Jan Cools

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 15235 views
Discussion

Assura selected rule checking

Category: Custom IC Design

By VaibhavAR

$usertype
•
updated over 7 years ago by Quek

4 replies • 14679 views
Discussion

CDL import with SpiceIn: W + L wrong!

Category: Custom IC Design

By bdjones1

$usertype
•
updated over 7 years ago by Andrew Beckett

4 replies • 20712 views
Discussion

Verilog A to symbol

Category: Custom IC Design

By Shobhitkareer

$usertype
•
updated over 7 years ago by Andrew Beckett

19 replies • 26543 views
Discussion

Multiple flight wires to symbol terminal

Category: Custom IC Design

By alecadair

$usertype
•
updated over 7 years ago by Andrew Beckett

3 replies • 15814 views
Discussion

Difference between V(P1,T1) <+ 0; and V(P1) <+ V(T1); in verilog A when they are used in 'if -else statement'

Category: Custom IC Design

By KiranTej

$usertype
•
updated over 7 years ago by Andrew Beckett

11 replies • 9648 views
Discussion

ADE XL new test addition on a running simulation

Category: Custom IC Design

By VEVAD

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 13465 views
Discussion

How to use rand_bit_stream for trasimpedance amplifier ?

Category: Custom IC Design

By salar1991

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 14277 views
Discussion

Virtuoso L and virtuoso xl cost ?

Category: Custom IC Design

By Marben

$usertype
•
updated over 7 years ago by Marben

2 replies • 17670 views
Discussion

problem with resistor in corner analysis

Category: Custom IC Design

By salar1991

$usertype
•
updated over 7 years ago by salar1991

2 replies • 14852 views
Discussion

ade explorer set instance value

Category: Custom IC Design

By rfham

$usertype
•
updated over 7 years ago by Andrew Beckett

5 replies • 15753 views
Discussion

Export transient waveform into ASCI/CSV format for psfxl simulation data

Category: Custom IC Design

By slim15

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 1495 views
Discussion

QRC conflictiong name spaces

Category: Custom IC Design

By fmele

$usertype
•
updated over 7 years ago by Saloni Chhabra

3 replies • 15064 views
Discussion

Assura LVS for Standard Cell Library with only Abstract View

Category: Custom IC Design

By alperro

$usertype
•
updated over 7 years ago by Quek

4 replies • 15353 views
Discussion

Transient DC voltage setup

Category: Custom IC Design

By AllenD

$usertype
•
updated over 7 years ago by Frank Wiedmann

3 replies • 17382 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.