Custom IC Design

Latest Posts

Discussion

Magnitude value in AC simulation with Cadence Virtuoso

Category: Custom IC Design

By Senan

$usertype
•
updated over 2 years ago by ShawnLogan

11 replies • 21711 views
Discussion

Convolution function of two temporal signals in Cadence Verilog-A

Category: Custom IC Design

By cheedyliew

$usertype
•
started over 2 years ago

0 replies • 7144 views
Discussion

Design and placement of hard macros

Category: Custom IC Design

By toufiqhanik

$usertype
•
started over 2 years ago

0 replies • 7480 views
Discussion

Failed to open the GUI of Cadence Abstract Generator

Category: Custom IC Design

By Hongming Lyu

$usertype
•
updated over 2 years ago by Alex Soyer

2 replies • 7717 views
Discussion

Which instance model parameters does Spectre save?

Category: Custom IC Design

By Brad RFeng

$usertype
•
updated over 2 years ago by Andrew Beckett

7 replies • 9740 views
Discussion

Running OCEAN XL sweep with a netlist instead of a lib/cel/view

Category: Custom IC Design

By AncisMichele

$usertype
•
updated over 2 years ago by Andrew Beckett

8 replies • 3577 views
Discussion

Behavioral modelling using verilogA for a TIA

Category: Custom IC Design

By TUKA

$usertype
•
updated over 2 years ago by TUKA

3 replies • 8521 views
Discussion

Layout output pins changing the behaviour of extracted netlist

Category: Custom IC Design

By Andres S

$usertype
•
started over 2 years ago

0 replies • 7340 views
Discussion

Adexl - interactive history does not display design variables

Category: Custom IC Design

By firebolt

$usertype
•
updated over 2 years ago by firebolt

2 replies • 1426 views
Discussion

SOA Warnings

Category: Custom IC Design

By PhilCGD

$usertype
•
updated over 2 years ago by Andrew Beckett

2 replies • 10111 views
Discussion

CIW save display information - unbale to get rid of this popup when closing ciw

Category: Custom IC Design

By firebolt

$usertype
•
updated over 2 years ago by firebolt

2 replies • 1675 views
Discussion

Bode Plot stability analysis for nonminimum phase systems

Category: Custom IC Design

By ronaldomponte

$usertype
•
updated over 2 years ago by ronaldomponte

4 replies • 9782 views
Discussion

Adexl Calculator - finding delay between 2 signals

Category: Custom IC Design

By firebolt

$usertype
•
updated over 2 years ago by firebolt

3 replies • 6989 views
Discussion

License installation issue

Category: Custom IC Design

By ArbLouis

$usertype
•
updated over 2 years ago by Andrew Beckett

1 replies • 7908 views
Discussion

VerilogA for staircase voltage generator issue

Category: Custom IC Design

By NewScreenName

$usertype
•
updated over 2 years ago by Andrew Beckett

4 replies • 9733 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.