Custom IC Design

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Discussion

how to calculate THD ??

Category: Custom IC Design

By Muffassir

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updated over 6 years ago by Cdub

12 replies • 32083 views
Discussion

Monte Carlo Ocean XL: can not delete history in a loop

Category: Custom IC Design

By Martyniuk

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updated over 6 years ago by Martyniuk

3 replies • 16702 views
Discussion

How to add an accurate triggered clock in a testbench

Category: Custom IC Design

By RFStuff

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updated over 6 years ago by Andrew Beckett

3 replies • 16612 views
Discussion

spectre terminated prematurely due to fatal error.

Category: Custom IC Design

By hTmTech

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updated over 6 years ago by Andrew Beckett

7 replies • 27663 views
Discussion

Maestro: Use Simulation sweep variable in output equation

Category: Custom IC Design

By HoWei

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updated over 6 years ago by Andrew Beckett

8 replies • 21493 views
Discussion

PVS floating license

Category: Custom IC Design

By sjeur

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updated over 6 years ago by Andrew Beckett

6 replies • 17144 views
Discussion

Design migration tool

Category: Custom IC Design

By Faizan UL HAQ

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updated over 6 years ago by Andrew Beckett

21 replies • 41599 views
Discussion

Error during ADE spectre simulation

Category: Custom IC Design

By NorNand

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updated over 6 years ago by NorNand

12 replies • 23204 views
Discussion

DC OP calculation for voltage reference with Startup Circuit

Category: Custom IC Design

By Johanny Saenz

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updated over 6 years ago by FormerMember

3 replies • 16921 views
Discussion

Trouble using pPar with Spectre simulation

Category: Custom IC Design

By AlexandreBoyer

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updated over 6 years ago by Andrew Beckett

4 replies • 17771 views
Discussion

AMS simulation error after removing a verilogA cell from the testbench

Category: Custom IC Design

By RFStuff

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updated over 6 years ago by RFStuff

3 replies • 14457 views
Discussion

Verilog $random seems to be not random

Category: Custom IC Design

By HoWei

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updated over 6 years ago by Andrew Beckett

2 replies • 18784 views
Discussion

Unable to descend into any of the views defined in the view list, 'auCdl schematic'

Category: Custom IC Design

By musabfarooq

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updated over 6 years ago by Andrew Beckett

1 replies • 5359 views
Discussion

Dots instead of solid lines when plotting corners

Category: Custom IC Design

By Roman K

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updated over 6 years ago by FormerMember

1 replies • 15235 views
Discussion

Unreasonable numbers and contributors seen in ADE-L Spectre noise summary

Category: Custom IC Design

By mmVivek

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updated over 6 years ago by mmVivek

2 replies • 14902 views

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