Custom IC Design

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Discussion

Floorplanner generate physical hierarchy

Category: Custom IC Design

By RVERP

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started over 8 years ago

0 replies • 13598 views
Discussion

[ADE XL] Compiling verilog-A module

Category: Custom IC Design

By Seokhyun Jeong

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started over 8 years ago

0 replies • 14230 views
Discussion

Layout XL: how to set default options for Selection Protection?

Category: Custom IC Design

By dontpanic

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updated over 8 years ago by dontpanic

4 replies • 16532 views
Discussion

How to subtract a wire/path from a polygon

Category: Custom IC Design

By JWHoll

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updated over 8 years ago by Andrew Beckett

1 replies • 3863 views
Discussion

QRC (EXT91) always fails

Category: Custom IC Design

By Zach

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updated over 8 years ago by Quek

6 replies • 17293 views
Discussion

How to store a value/Store function in Verilog-A/AMS

Category: Custom IC Design

By Hasan91

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updated over 8 years ago by Hasan91

2 replies • 2240 views
Discussion

IQ cross-talk: simulation artefact?

Category: Custom IC Design

By itos

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updated over 8 years ago by itos

4 replies • 15820 views
Discussion

Error while simulating verilog-A block

Category: Custom IC Design

By tangudubharat

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updated over 8 years ago by tangudubharat

6 replies • 17585 views
Discussion

Sampled point inaccuracy in AMS simulation

Category: Custom IC Design

By auran

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updated over 8 years ago by auran

4 replies • 16178 views
Discussion

VHDL-AMS library issue?

Category: Custom IC Design

By srana01

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updated over 8 years ago by Andrew Beckett

1 replies • 15287 views
Discussion

ADE-XL doesn't pick up readic initial condition file/ How to properly pass initial condition setup into ADEXL?

Category: Custom IC Design

By RFAnalog123

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updated over 8 years ago by Andrew Beckett

2 replies • 3621 views
Discussion

Virtuoso Spice In grouping instances

Category: Custom IC Design

By shredds

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updated over 8 years ago by shredds

2 replies • 14164 views
Discussion

dcOp sweep

Category: Custom IC Design

By drdanmc

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updated over 8 years ago by Andrew Beckett

3 replies • 17738 views
Discussion

Extract single net from layout

Category: Custom IC Design

By drdanmc

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updated over 8 years ago by Andrew Beckett

1 replies • 14933 views
Discussion

vsin frequency precision, and tips for coherent sampling

Category: Custom IC Design

By msharma

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updated over 8 years ago by msharma

2 replies • 15577 views

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