Custom IC Design

Latest Posts

Discussion

Transient Simulation of AMS gives convergence error

Category: Custom IC Design

By ashrafSazid

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 15874 views
Discussion

Create Vias: shapes, drawn areas

Category: Custom IC Design

By JWHoll

$usertype
•
updated over 8 years ago by Quek

1 replies • 16022 views
Discussion

Oversampling clock and data recovery for SerDes communication

Category: Custom IC Design

By bitan1990

$usertype
•
started over 8 years ago

0 replies • 13859 views
Discussion

Modify the resistivity of M1

Category: Custom IC Design

By samer1

$usertype
•
updated over 8 years ago by samer1

8 replies • 15585 views
Discussion

what is the use of data.dm and constraint in each design directory?

Category: Custom IC Design

By Qilong

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 28533 views
Discussion

VIVA: how to disable automatic displaying of variables when hovering over trace names?

Category: Custom IC Design

By dontpanic

$usertype
•
updated over 8 years ago by dontpanic

4 replies • 14534 views
Discussion

Change a technology library into a design library

Category: Custom IC Design

By Qilong

$usertype
•
updated over 8 years ago by Qilong

2 replies • 19276 views
Discussion

how to find total capcitance of mosfet(pmos or nmos)?

Category: Custom IC Design

By pavan261995

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 1047 views
Discussion

anaName in OCEAN analysis not working

Category: Custom IC Design

By leok

$usertype
•
updated over 8 years ago by leok

2 replies • 13859 views
Discussion

QRC extraction problem

Category: Custom IC Design

By umais

$usertype
•
updated over 8 years ago by Andrew Beckett

3 replies • 15589 views
Discussion

Problem saving intrinsic parameters using save statement save NM0:all

Category: Custom IC Design

By Bean1234

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 1831 views
Discussion

Storing config of a cell in a file/cellview

Category: Custom IC Design

By itos

$usertype
•
updated over 8 years ago by Andrew Beckett

3 replies • 2058 views
Discussion

BER test setup in cadence

Category: Custom IC Design

By EngrZM

$usertype
•
started over 8 years ago

0 replies • 13931 views
Discussion

Cadence Virtuoso: Import a large verilog netlist to cadence schematic

Category: Custom IC Design

By oAwad

$usertype
•
updated over 8 years ago by Andrew Beckett

3 replies • 18936 views
Discussion

layout dynamic selection accessibility?

Category: Custom IC Design

By yeh1

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 13878 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.