Custom IC Design

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problem with strobe period

Category: Custom IC Design

By Medya
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updated over 4 years ago by Andrew Beckett

5 replies • 20203 views
Discussion

convert selected signed out signal to unsigned

Category: Custom IC Design

By abdurrahman0234
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updated over 4 years ago by Andrew Beckett

1 replies • 11018 views
Discussion

ViVa is plotting old simulation result instead of the current simulation results

Category: Custom IC Design

By RFStuff
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updated over 4 years ago by JainN

4 replies • 11762 views
Discussion

2-stage CMOS OTA: LVS errors

Category: Custom IC Design

By Jose Sarmento
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updated over 4 years ago by Jose Sarmento

1 replies • 10511 views
Discussion

SOLVED - Problem to avoid the removal of some capacitors with low values with Spectre XPS tool while performing transient analysis

Category: Custom IC Design

By VitorLima
•
updated over 4 years ago by MaximX

3 replies • 1601 views
Discussion

Backup and reload results in Assembler

Category: Custom IC Design

By shadiyoussef
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updated over 4 years ago by shadiyoussef

4 replies • 13022 views
Discussion

Sine wave amplitude-modulated by a ramp for transient simulation

Category: Custom IC Design

By maaz2020
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updated over 4 years ago by maaz2020

2 replies • 14217 views
Discussion

Swap Activity Warning: Excessive swap activity

Category: Custom IC Design

By RavitejKammari
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updated over 4 years ago by Andrew Beckett

1 replies • 16239 views
Discussion

Question about exporting simulation results to csv format, with ocean script

Category: Custom IC Design

By dskang
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updated over 4 years ago by dskang

8 replies • 16800 views
Discussion

FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit

Category: Custom IC Design

By bikram94
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updated over 4 years ago by bikram94

2 replies • 13784 views
Discussion

order of output evaluation in maestro results pane

Category: Custom IC Design

By sergeiGorbikov
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updated over 4 years ago by Andrew Beckett

7 replies • 6502 views
Discussion

Verilog-A: How to trigger event, if input parameter changes in DC sweep

Category: Custom IC Design

By NZimmermann
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updated over 4 years ago by Andrew Beckett

5 replies • 14036 views
Discussion

Error When Running AMS Simulations with Both VHDL and Verilog in Digital Heirarchy

Category: Custom IC Design

By amrao
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updated over 4 years ago by amrao

3 replies • 11865 views
Discussion

Cadence Liberate CCS Power Characterization Accuracy

Category: Custom IC Design

By anurans
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updated over 4 years ago by anurans

4 replies • 12563 views
Discussion

Is there leakage current in Analoglib's cap?

Category: Custom IC Design

By yysunj
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updated over 4 years ago by Andrew Beckett

1 replies • 997 views

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